Intel Pentium ("P5") Case Study

• 1993
• executes up to two x86 instructions per cycle
• two integer pipelines (U and V) and floating-point pipeline
• five-stage integer pipelines - combined fetch and D1 stages that then split into two integer segments (consisting of D2/EX/WB stages) which operate in lockstep (although U can have early EX->WB transition if V pipe stalls)
  • fetch - fetch 32 bytes of instructions from the physically-addressed 2-way set associative 8 KB icache into a prefetch buffer; use the two 32-byte buffers in a double buffered manner or use one for prefetching down a predicted-taken branch target path
  • D1 - dual decoders determine instruction length and check for dual issue; single issue occurs down the U pipeline for complex instructions including floating-point, jumps in the first issue position, and dependent instruction pairs in general; special dual issue is provided for pairing a flag-setting instruction with a conditional jump and pairing pushes and pops (helpful for procedure entry/exit)
  • D2 - can read two registers or handle displacement and immediate in one cycle
  • EX - some integer instructions (shift, rotate) only done in U pipeline; floating-point instructions and integer multiply are initiated in a separate floating-point pipeline by the EX stage of the U pipeline; both pipes can access the data cache (see below)
  • WB - write back to registers
• on the original Pentium design the branches are predicted according to a 256-entry branch target buffer (each entry contains inst. address, target address, and two bits of history); Pentium w/ MMX uses a scheme similar to the Pentium Pro method (see below) and adds an extra stage to the pipeline to do this
• physically-addressed 2-way set associative 8 KB data cache is implemented with dual-ported TLB and tags and with 8-way interleaved data storage; allows parallel access by U and V pipelines as long as there is no bank conflict
• chip architects were Don Alpert (chief), Jack Mills, Bob Dreyer, Ed Grohoski, and Uri Weiser
• D. Alpert and D. Avnon, "Architecture of the Pentium Microprocessor," IEEE Micro, June 1993, pp. 11-21.