Intel P6 Case Study

• design started in 1990
• Pentium Pro - 1995, P6 core
• Pentium II - 1997, P6 core + MMX
• Pentium III - 1999, P6 core + MMX + SSE
• decoupled microarchitecture: translates x86 instructions into internal uops (micro-operations)
• pipeline organization
  • 8-stage in-order pipeline - decodes up to three x86 insts. per cycle, but only one can be complex (e.g., memory-to-reg); each x86 inst. is translated into one or more fixed-length uops; uops are placed into 20-entry reservation station
  • 3-stage out-of-order core - issue up to four uops per cycle, results from completed uops written to 40-entry reorder buffer
  • 3-stage retirement pipeline - retire up to three uops per cycle

                   front-end                execution core      back-end        
                   ---------                --------------      --------
                                                                
                   I1 - next IP
          1   .--> I2 - Icache 1
          2   |    I3 - Icache 2 / ILD
          3   |    I4 - Decode 1 / rotate
          4   |    I5 - Decode 2
          5   |    I6 - Decode 3
          6   |    I7 - Register rename
          7   |    I8 - RS write
          8   |                             O1 - RS schedule
          9   |                             O2 - RS dispatch
         10   `---- branch mispredict ----- O3 - execute
                                                                R1 - Retire 1
                                                                R2 - Retire 2
                                                                R3 - RRF write
        

• branch prediction
  • 512-entry, 4-way set-associative BTB using PAs prediction scheme (4-bit per-address BHSRs stored in the BTB entries index into one of four 16-entry PHTs); correct prediction of untaken yields no penalty, correct prediction of taken yields one cycle stall, misprediction yields 10-15 cycle penalty
  • decoder "shortstop" predicts branch based on its displacement when it is not in BTB; untaken forward branches yield no penalty, taken backward branches yield 5-6 cycle penalty, misprediction yields 10-15 cycle penalty
• register-renaming for three uops per cycle to avoid WAR and WAW dependencies
• uop scheduling takes into account forwarding paths
• on-chip L1 and L2 caches; L1 is pseudo-dual-ported 8 KB (4 interleaved banks) with 2-cycle hit; L2 is 256 KB, 512 KB, or 1 MB, runs at processor clock speed, L1 miss/L2 hit is 6 cycles
• chip architects were Bob Colwell (chief), Glenn Hinton (senior), Dave Papworth (senior), Michael Fetterman, and Andy Glew
• R. Colwell, et al., "Intel's P6 Microarchitecture," chapter 7 in Shen and Lipasti textbook
• D. Papworth, "Tuning the Pentium Pro microarchitecture," Computer, April 1996, pp. 8-15.