CPSC 330 Fall 2004 Program 2 due by 4:00 on Friday, November 5 For this assignment, you may work in teams of two to write an SRC pipeline simulator. You should implement the following instructions: la (:=op=5) -> R[ra] <- disp: // load displacement address add (:=op=12) -> R[ra] <- R[rb] + R[rc]: addi (:=op=13) -> R[ra] <- R[rb] + c2<16..0>{sign ext., 2's compl.}: sub (:=op=14) -> R[ra] <- R[rb] - R[rc]: neg (:=op=15) -> R[ra] <- -R[rc]: and (:=op=20) -> R[ra] <- R[rb] ^ R[rc]: andi (:=op=21) -> R[ra] <- R[rb] ^ c2<16..0>{sign extend}: or (:=op=22) -> R[ra] <- R[rb] | R[rc]: ori (:=op=23) -> R[ra] <- R[rb] | c2<16..0>{sign extend}: not (:=op=24) -> R[ra] <- ~R[rc]: nop (:=op=0) -> : // no operation stop (:=op=31) -> Run <- 0 // stop instruction Follow the steps of Figure 5.6. However, you should note that each stage should act independently and that pipeline latch register changes in one stage should not affect the next stage until the next cycle. (E.g., an assignment to X3 in the decode stage should not affect the ALU stage until the following cycle.) Input will be given as decimal quads: opcode, ra, rb, (rc or c2) (Input should be obtained from stdin, allowing I/O redirection.) Processing ends with the writeback stage of a stop instruction. You should implement a register scoreboard to handle register dependencies. Output should be: 1) a trace as given in homework 5 2) a stairstep diagram for the first 50 cycles You may use any language that can be easily compiled and run on a departmental Sun workstation. Extra credit _may_ be given for visual impression and clarity. (Note: extra credit is not guaranteed, but will be awarded based on my subjective opinion of your program's visually demonstrative value as to how conveying how a pipeline works with the least distraction. E.g., just throwing up Java boxes using the Homework 4 pipeline state diagrams will likely not be enough to earn extra credit.) Example input file 5 1 0 -1 13 2 1 5 5 3 1 -2 12 4 2 3 31 0 0 0 output cycle 1: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 0 | PC_in: 4 - - - - - - - +-----+ 1 IF: IR2_in: la r1,-1(r0) PC2_in: 4 +------------------+ +-----+ IF/ID:- - - - IR2| empty | - -PC2| 0 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: | | +---------------------------------------------+ IR3_in: empty X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| empty |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: empty Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| empty |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: empty Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| empty |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 0 0 0 0 0 cycle 2: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 4 | PC_in: 8 - - - - - - - +-----+ 1 IF: IR2_in: addi r2,r1,5 PC2_in: 8 +------------------+ +-----+ IF/ID:- - - - IR2| la r1,-1(r0) | - -PC2| 4 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: | | +---------------------------------------------+ IR3_in: la r1 X3_in: 0 Y3_in: -1 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| empty |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: empty Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| empty |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: empty Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| empty |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 1 0 0 0 0 0 0 cycle 3: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 8 | PC_in: 12 - - - - - - - +-----+ 1 IF: IR2_in: la r3,-2(r1) PC2_in: 12 +------------------+ +-----+ IF/ID:- - - - IR2| addi r2,r1,5 | - -PC2| 8 | - - - - - - - - - - - - - +------------------+ +-----+ ********* +---------------------------------------------+ 2 ID: * STALL * | | ********* +---------------------------------------------+ IR3_in: X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| la r1 |- - - - - - X3| 0 |- - -Y3| -1 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: `----------------->alufn: add IR4_in: la r1 Z4_in: -1 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| empty |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: empty Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| empty |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 1 0 0 0 0 0 0 cycle 4: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 8 | PC_in: 12 - - - - - - - +-----+ 1 IF: IR2_in: la r3,-2(r1) PC2_in: 12 +------------------+ +-----+ IF/ID:- - - - IR2| addi r2,r1,5 | - -PC2| 8 | - - - - - - - - - - - - - +------------------+ +-----+ ********* +---------------------------------------------+ 2 ID: * STALL * | | ********* +---------------------------------------------+ IR3_in: X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| la r1 |- - - - - - - - - - Z4| -1 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: la r1 Z5_in: -1 +-----------+ +----+ MEM/WB: - - - IR5| empty |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 1 0 0 0 0 0 0 cycle 5: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 8 | PC_in: 12 - - - - - - - +-----+ 1 IF: IR2_in: la r3,-2(r1) PC2_in: 12 +------------------+ +-----+ IF/ID:- - - - IR2| addi r2,r1,5 | - -PC2| 8 | - - - - - - - - - - - - - +------------------+ +-----+ ********* +---------------------------------------------+ 2 ID: * STALL * write | a3: r1 R3: -1 | ********* +---------------------------------------------+ IR3_in: X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| la r1 |- - - - - - - - - - Z5| -1 |- - - - - - - - - - +-----------+ +----+ 5 WB: `-----> write r1 register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | -1 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 0 0 0 0 0 cycle 6: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 8 | PC_in: 12 - - - - - - - +-----+ 1 IF: IR2_in: la r3,-2(r1) PC2_in: 12 +------------------+ +-----+ IF/ID:- - - - IR2| addi r2,r1,5 | - -PC2| 8 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: read | a1: r1 R1: -1 | +---------------------------------------------+ IR3_in: addi r2 X3_in: -1 Y3_in: 5 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | -1 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 1 0 0 0 0 0 cycle 7: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 12 | PC_in: 16 - - - - - - - +-----+ 1 IF: IR2_in: add r4,r2,r3 PC2_in: 16 +------------------+ +-----+ IF/ID:- - - - IR2| la r3,-2(r1) | - -PC2| 12 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: read | a1: r1 R1: -1 | +---------------------------------------------+ IR3_in: la r3 X3_in: -1 Y3_in: -2 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| addi r2 |- - - - - - X3| -1 |- - -Y3| 5 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: `----------------->alufn: add IR4_in: addi r2 Z4_in: 4 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | -1 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 1 1 0 0 0 0 cycle 8: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 16 | PC_in: 20 - - - - - - - +-----+ 1 IF: IR2_in: stop r0,r0,r0 PC2_in: 20 +------------------+ +-----+ IF/ID:- - - - IR2| add r4,r2,r3 | - -PC2| 16 | - - - - - - - - - - - - - +------------------+ +-----+ ********* +---------------------------------------------+ 2 ID: * STALL * | | ********* +---------------------------------------------+ IR3_in: X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| la r3 |- - - - - - X3| -1 |- - -Y3| -2 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: `----------------->alufn: add IR4_in: la r3 Z4_in: -3 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| addi r2 |- - - - - - - - - - Z4| 4 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: addi r2 Z5_in: 4 +-----------+ +----+ MEM/WB: - - - IR5| |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | -1 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 1 1 0 0 0 0 cycle 9: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 16 | PC_in: 20 - - - - - - - +-----+ 1 IF: IR2_in: stop r0,r0,r0 PC2_in: 20 +------------------+ +-----+ IF/ID:- - - - IR2| add r4,r2,r3 | - -PC2| 16 | - - - - - - - - - - - - - +------------------+ +-----+ ********* +---------------------------------------------+ 2 ID: * STALL * write | a3: r2 R3: 4 | ********* +---------------------------------------------+ IR3_in: X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| la r3 |- - - - - - - - - - Z4| -3 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: la r3 Z5_in: -3 +-----------+ +----+ MEM/WB: - - - IR5| addi r2 |- - - - - - - - - - Z5| 4 |- - - - - - - - - - +-----------+ +----+ 5 WB: `-----> write r2 register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | -1 | 4 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 1 0 0 0 0 cycle 10: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 16 | PC_in: 20 - - - - - - - +-----+ 1 IF: IR2_in: stop r0,r0,r0 PC2_in: 20 +------------------+ +-----+ IF/ID:- - - - IR2| add r4,r2,r3 | - -PC2| 16 | - - - - - - - - - - - - - +------------------+ +-----+ ********* +---------------------------------------------+ 2 ID: * STALL * write | a3: r3 R3: -3 | ********* +---------------------------------------------+ IR3_in: X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| la r3 |- - - - - - - - - - Z5| -3 |- - - - - - - - - - +-----------+ +----+ 5 WB: `-----> write r3 register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | -1 | 4 | -3 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 0 0 0 0 0 cycle 11: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 16 | PC_in: 20 - - - - - - - +-----+ 1 IF: IR2_in: stop r0,r0,r0 PC2_in: 20 +------------------+ +-----+ IF/ID:- - - - IR2| add r4,r2,r3 | - -PC2| 16 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: read | a1: r2 R1: 4 a2: r3 R2: -3 | +---------------------------------------------+ IR3_in: add r4 X3_in: 4 Y3_in: -3 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | -1 | 4 | -3 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 0 1 0 0 0 cycle 12: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 20 | PC_in: 24 - - - - - - - +-----+ 1 IF: IR2_in: empty PC2_in: 24 +------------------+ +-----+ IF/ID:- - - - IR2| stop r0,r0,r0 | - -PC2| 20 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: | | +---------------------------------------------+ IR3_in: stop r0 X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| add r4 |- - - - - - X3| 4 |- - -Y3| -3 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: `----------------->alufn: add IR4_in: add r4 Z4_in: 1 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | -1 | 4 | -3 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 0 1 0 0 0 cycle 13: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 24 | PC_in: 28 - - - - - - - +-----+ 1 IF: IR2_in: empty PC2_in: 28 +------------------+ +-----+ IF/ID:- - - - IR2| empty | - -PC2| 24 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: | | +---------------------------------------------+ IR3_in: empty X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| stop r0 |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: stop r0 Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| add r4 |- - - - - - - - - - Z4| 1 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: add r4 Z5_in: 1 +-----------+ +----+ MEM/WB: - - - IR5| |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | -1 | 4 | -3 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 0 1 0 0 0 cycle 14: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 28 | PC_in: 32 - - - - - - - +-----+ 1 IF: IR2_in: empty PC2_in: 32 +------------------+ +-----+ IF/ID:- - - - IR2| empty | - -PC2| 28 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: write | a3: r4 R3: 1 | +---------------------------------------------+ IR3_in: empty X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| empty |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: empty Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| stop r0 |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: stop r0 Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| add r4 |- - - - - - - - - - Z5| 1 |- - - - - - - - - - +-----------+ +----+ 5 WB: `-----> write r4 register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | -1 | 4 | -3 | 1 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 0 0 0 0 0 cycle 15: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 32 | PC_in: 36 - - - - - - - +-----+ 1 IF: IR2_in: empty PC2_in: 36 +------------------+ +-----+ IF/ID:- - - - IR2| empty | - -PC2| 32 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: | | +---------------------------------------------+ IR3_in: empty X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| empty |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: empty Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| empty |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: empty Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| stop r0 |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | -1 | 4 | -3 | 1 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 0 0 0 0 0 fetch count is 5 cycle diagram | 11111111112222222222333333333344444444445 ....................|12345678901234567890123456789012345678901234567890 la r1,-1(r0) |FDAMW . . . . . . . . . addi r2,r1,5 | F---DAMW. . . . . . . . . la r3,-2(r1) | F---DAMW . . . . . . . . add r4,r2,r3 | . F---DAMW. . . . . . . . stop r0,r0,r0 | . F---DAMW . . . . . . .