CPSC 330 - Fall 2006 Homework 2 Due by class time on Friday, October 20 1. Question 5.4 of your textbook, p. 361. 2. Question 5.5 of your textbook, p. 361. 3. Question 5.7 (a) of your textbook, p. 362. 4. Question 5.13 (a,b,c) of your textbook, p. 363. 5. Question 7.4 of your textbook, p. 446. 6. Question 7.5 (a,b) of your textbook, p. 446. 7. Question 7.7 of your textbook, p. 446. 8. Consider a 4 GB byte-addressable main memory with a two-way set-associative cache of 512 KB and 16 bytes per line. a) How many total lines are there in cache? (not just per bank) b) Identify the main memory address fields and sizes. c) How many comparators must operate in parallel to perform tag-matching? 9. The HP7200 has a large direct-mapped data cache off-chip. On the chip it has a 64-line fully associative assist cache (data only). The assist cache is searched in parallel with the off-chip data cache. Misses cause refills to be directed to the assist cache, which has FIFO replacement. a) What problem with direct-mapped caches does the assist cache solve? Explain your answer. There is a hint bit the load/store instructions of the HP7200 that indicates that the data being accessed will have spatial locality only. This bit is attached to the line in the assist cache when the line is first brought in. If the spatial locality bit is on, then a line being replaced in assist cache is _not_ placed in external cache. If the bit is off, then the replaced line is written into the external cache. b) How can this hint bit improve performance? 10. Consider an 8 KB direct-mapped, write-back, write-allocate cache with 32-byte lines. Which of these two program segments will be faster? Explain your choice. (note: c[][] is stored in row-major order.) #define N 1024 #define N 1024 double c[N][N]; double c[N][N]; sum = 0.0; sum = 0.0; for(i=0; i