CPSC 330 - Fall 2008 Homework 3 Due by class time on Wednesday, October 15 Example: +----------+ +---------------+ +-------------+ | source |--|>-------bus------| combinational |--------| destination | | register | | | logic | .--| register | +----------+ | +---------------+ | +-------------+ R_out R_in |<---propagation---->|<----logic---->|<--setup-->|<--hold-->| | delay for bus delay time time | | | |<----------------minimum clock cycle time----------------->| For clock timing, you find the delay time along the longest active path in a datapath. Delays can typically be separately idenitifed, as done in the diagram above. Then, for example, if each identified component of the delay time is 1 nsec, the minimum clock cycle time would be 4 nsec, and the maximum clock rate would be 250 MHz. 1. Assume that propagation delays along the bus, through the ALU, and through the mux of Figure 7.1 are 0.3, 1.5, and 0.1 ns respectively. The setup time for the registers is 0.1 ns, and the hold time is 0.1 ns. What is the minimum clock period needed? Example: Give the control sequence for a two-word instruction ADD NUM,R1 as executed on the datapath of Figure 7.1. (For background on the instruction set, see sections 2.4-2.6 in your textbook) (alternate resource: Dr. John Lee's course notes based on our textbook: http://www.ece.iupui.edu/~johnlee/ECE365/pdfs/Chapter7-ProcessingUnit.pdf) ADD NUM,R1 // R1 <- R1 + memory[NUM] 1. PCout, MARin, Read, Select4, Add, Zin // MAR<-PC, read, Z<-PC+4 // read of opcode word 2. Zout, PCin, Yin, WMFC // PC,Y<-Z // note Y loaded for branching 3. MDRout, IRin // IR<-MDR 4. PCout, MARin, Read, Select4, Add, Zin // MAR<-PC, read, Z<-PC+4 // read of address word 5. Zout, PCin, Yin, WMFC // PC,Y<-Z 6. MDRout, MARin, Read // MAR<-MDR, read // read of data word 7. R1out, Yin, WMFC // Y<-R1 8. MDRout, SelectY, Add, Zin // Z<-R1+MDR 9. Zout, R1in, End // R1<-Z 2. Question 7.5 (a,c) of your textbook, p. 446. Write the sequence of control steps required for the bus structure of Figure 7.1 for each of the following instructions: (a) is ADD #NUM,R1 or ADDI NUM,R1 (add immediate to R1) // R1 <- R1 + NUM +-----------------------+ | ADD | immediate mode | +-----------------------+ | NUM | +-----------------------+ (c) is ADD (NUM),R1 (memory indirect add to R1, where memory[NUM] contains a pointer) // R1 <- R1 + memory[memory[NUM]] +-----------------------+ | ADD | memory indirect | +-----------------------+ | NUM | +-----------------------+ Assume that each instruction consists of two words. The first word specifies the operation and addressing mode, and the second word contains the number or memory address NUM. 3. For the datapath of Figure 7.1, (a) Give the control sequence for a PDP-8-like jump to subroutine instruction, which stores the return address in the first word of the subroutine and then sets the program counter to the second word of the subroutine. JMS ADDR // jump to subroutine = memory[ADDR] <- updated_pc; // pc <- ADDR + 4; +-----------------------+ | JMS | memory direct | +-----------------------+ | ADDR | +-----------------------+ (b) Give the control sequence for a PDP-8-like indirect jump, which was used for subroutine returns (since an indirect jump to the first word of a subroutine will load the previously-stored return address into the program counter). JMP (ADDR) // jump indirect = pc <- memory[ADDR]; +-----------------------+ | JMP | memory indirect | +-----------------------+ | ADDR | +-----------------------+ Assume both instructions are two words, in which the first word specifies the operation and addressing mode, and the second word contains the memory address ADDR. You may omit the first three time steps from your answers for (a) and (b) if you explain the basis for the omission. Please annotate each set of control signals with concrete RTN, as illustrated by the example above.