CPSC 3300 - Fall 2014
Homework 2
Due Monday, Sept. 29
Each student must turn in a separate set of homework solutions,
but you may work together in study groups with other students
from the class. Include the names of your study group members
on the solution set you submit.
Also, please provide sufficient space for your calculations and
answers so that grading will be easier.
1. B.6 - Show NAND is universal by implementing (a) 2-input AND,
(b) 2-input OR, and (c) 1-input NOT functions with one
or more 2-input NAND gates.
2. Three 2-input AND gates can be arranged in either a tree-like
or cascade pattern to implement a four-input AND function. Show
how you can implement a four-input NAND function using only
2-input logic gates.
3. Give the simplified logic expressions for segments E, F, and G
in a seven-segment display.
Digit Code Segments
WXYZ A B C D E F G
0 0000 1 1 1 1 1 1 0 ---A---
1 0001 0 1 1 0 0 0 0 | |
2 0010 1 1 0 1 1 0 1 F B
3 0011 1 1 1 1 0 0 1 | |
4 0100 0 1 1 0 0 1 1 ---G---
5 0101 1 0 1 1 0 1 1 | |
6 0110 1 0 1 1 1 1 1 E C
7 0111 1 1 1 0 0 0 0 | |
8 1000 1 1 1 1 1 1 1 ---D---
9 1001 1 1 1 1 0 1 1
4. B.11
5. B.12
6. Design a modulo-3 counter using two D flip-flops with the states
cycling as 00,01,10,00,01,.... (There is no input.) Use a truth
table with four columns, and use "don't care" values where
appropriate.
QA(t) QB(t) | QA(t+1) QB(t+1)
------------+----------------
Simplify the logic expressions for the next state values, and
draw the resulting circuit.
7. Design a modulo-3 up counter using two JK flip-flops and a single
"up" input. The state cycles as 00,01,10,00,01,... when up=1. The
state remains the same when up=0. Use a truth table with nine
columns:
up QA(t) QB(t) | JA KA JB KB | QA(t+1) QB(t+1)
---------------+-------------+----------------
Start by filling the first three and last two columns. Then use
the JK excitation table to fill in the four JK columns. Simplify
the logic expressions for the four JK values, and draw the
resulting circuit.
8. Add a synchronous "reset" control signal to your modulo-3 up
counter. Use the technique described in the notes to add gates to
your previous circuit such that reset=1 will cause the next state
to be 00.