CPSC 3300 - Fall 2015 Study Guide for Exam 2 Coverage: CPU implementation 1. Be able to define or match these terms register internal CPU bus tri-state buffer CPU data path control control signal hardwired control microprogrammed control control store pipelining pipeline stages pipeline latches structural hazard data dependencies RAW (read after write ordering must be preserved) - true dependency WAR (write after read ordering must be preserved) - anti-dependency WAW (write after write ordering must be preserved) - output dependency load-use data hazard pipeline stall register scoreboard forwarding multi-ported register file control hazard (branch hazard) branch target address (BTA) branch taken branch not taken (untaken) delayed branch branch delay slot branch prediction misprediction misprediction recovery flushing pipeline stages dynamic branch prediction branch target address cache (BTAC) branch history table (BHT) branch target buffer (BTB) branch history shift register (BHSR) gshare branch prediction algorithm superscalar EPIC VLIW dependency checking register renaming instruction window (reservation stations) result window (reorder buffer) speculative execution out-of-order execution precise exceptions predication 2. Be able to: A. Given a high-level RTL or assembly language statement, give the necessary step-by-step RTL, control signals, and/or microcode to implement that statement on a given datapath. B. Identify critical path(s) in a datapath when implementing a high- level RTL statement or assembly-language instruction. C. Given a code sequence, draw a data dependency graph. D. Describe in general what each stage in the 5-stage pipeline does. E. Given a code sequence, identify where any stalls occur and determine their duration on the 5-stage pipeline. F. Given a code sequence, identify where any forwarding actions occur on the 5-stage pipeline. G. Given a code sequence, draw the pipeline cycle diagram (stairstep diagram) for that code executing on the 5-stage pipeline. H. Explain how data hazards are detected and how forwarding paths work. I. Draw forwarding paths on a pipeline diagram. J. Describe how delayed branches work in the 5-stage pipeline. K. Describe how a BTB (or BTAC and BHT) provides a predicted next instruction address for branch instructions. L. Calculate the specific or average CPI for a given branching scheme. Alternatively, calculate misprediction penalties. M. Explain how a reorder buffer provides for branch misprediction recovery when the processor implements speculative execution. N. Explain how a reorder buffer provides for precise exceptions when the processor implements out-of-order execution. O. Compare the benefits of superscalar versus VLIW processors. P. Give the "record of execution" VLIW program produced by a compiler for a short code sequence based on operation slots and operation latencies. (Will be similar to horizontal microcode.) Be prepared to work problems as given in homeworks 5 and 6.