* for 0 <= i <= (n-1), the value in R[i] may change only if R[i]_in is
asserted (specifically, the value on the shared bus in the middle of
Figure 2.23 is always available as the input to R[i], but R[i]_in must
be asserted for R[i] to get this value)
* the value in W may change only if W_in is asserted (specifically, the
value on the bus incremented by one is always available as the input
to W, but W_in must be asserted for W to get this value)
* the value in Y may change only if Y_in is asserted (specifically, the
value on the bus is always available as the input to Y, but Y_in must
be asserted for Y to get this value)
* the value in Z may change only if Z_in is asserted (specifically, the
value on the bus is always added with the value in Y, and the sum of
those two values is always available as the input to Z, but Z_in must
be asserted for Z to get this value)
* for 0 <= i <= (n-1), the value in R[i] is placed on the bus only if
R[i]_out is asserted
* the value in W is placed on the bus only if W_out is asserted
* the value in Z is placed on the bus only if Z_out is asserted
* only one value can be placed on the bus during a single cycle (i.e.,
only one X_out control signal can be asserted among all the sources X
connected to the bus -- X can be an R[i], W, or Z)