CPSC 330 - Fall 2005
Homework 3
Due by class time on Wednesday, September 28
Purpose:
(1) work with sequential logic
(2) work with RTL
1. Consider the unclocked JK latch.
(a) Redo the JK-latch truth table using don't care values as
appropriate for R and S. Draw the Karnaugh maps for R and
S with inputs JKQ and show that in simplified form :
_
R = KQ S = JQ
(b) Draw the circuit diagram for the unclocked JK latch using
two 2-input and gates and two 2-input nor gates.
(c) You can add a clock input C to each of the and gates.
_
R = KQC S = CJQ
Draw the circuit diagram for the clocked JK latch using
two 3-input and gates and two 2-input nor gates.
2. Find a circuit diagram for an edge-triggered JK flip flop. Draw
it (and cite your source). Identify whether it is positive
(leading) edge triggered or negative (trailing) edge triggered.
Briefly explain why this circuit needs to be more complicated
than the circuit you designed in (1c) above.
Example
A sequential circuit has one D flip-flop, two inputs X and Y,
and one output A. The combinational logic consists of two
cascaded xor gates with the output of the second gate being
used as the next state.
A = Q(t)
D_in = Q(t) xor (X xor Y)
.--------------------------.
| |
| +-----+ |
+-----+ `-->| | D_in +---+ Q |
X--->| | | xor |------->| |---*-----> A
| xor |------>| | | D |
Y--->| | +-----+ CLK->| |
+-----+ +---+
The truth table for this circuit is
current next
inputs state output state
X Y Q(t) | X xor Y | A D_in == Q(t+1)
---------------+-----------+-----------------------
0 0 0 | 0 | 0 0 0
0 0 1 | 0 | 1 1 1
0 1 0 | 1 | 0 1 1
0 1 1 | 1 | 1 0 0
1 0 0 | 1 | 0 1 1
1 0 1 | 1 | 1 0 0
1 1 0 | 0 | 0 0 0
1 1 1 | 0 | 1 1 1
or you may find it easier to order the table with the current
state listed first (the tables are equivalent)
current next
state inputs output state
Q(t) X Y | X xor Y | A D_in == Q(t+1)
----------------+-----------+-----------------------
0 0 0 | 0 | 0 0 0
0 0 1 | 1 | 0 1 1
0 1 0 | 1 | 0 1 1
0 1 1 | 0 | 0 0 0
1 0 0 | 0 | 1 1 1
1 0 1 | 1 | 1 0 0
1 1 0 | 1 | 1 0 0
1 1 1 | 0 | 1 1 1
The state diagram for this circuit as a Moore machine (where the
outputs are associated with the states) is:
01,10
.---. .-----------. .---.
/ v.===./ v.===./ \
00,11 | |0/0| |1/1| | 00,11
\ /`==='^ /`==='^ /
`---' `-----------' `---'
01,10
(Note that a part of this circuit is essentially a T flip-flop.)
3. A sequential circuit has one D flip-flop, two inputs X and Y, and
one output S. The combinational logic consists of a full adder
with the carry out being used as the next state.
+---------+
X ----->| | sum
| full |-----------------------> S
Y ----->| |
| adder | carry = D_in +---+ Q
.---->| |------------->| |---.
| +---------+ | D | |
| CLK->| | |
| +---+ |
| |
`--------------------------------------'
(a) Give the state table using X, Y, Q(t) yielding Q(t+1), S
current next
inputs state state output
X Y Q(t) | Q(t+1) S
---------------+---------------
0 0 0 | 0 0
0 0 1 | 0 1
0 1 0 | 0 1
0 1 1 | 1 0
1 0 0 | 0 1
1 0 1 | 1 0
1 1 0 | 1 0
1 1 1 | 1 1
(b) Give the state diagram as a Mealy machine (where the outputs are
associated with the transitions).
11/0
.---. .-----------. .---.
00/0, / v.===./ v.===./ \ 01/0
01/1, | | 0 | | 1 | | 10/0
10/1 \ /`==='^ /`==='^ / 11/1
`---' `-----------' `---'
00/1
[This is basis of a serial (bit-by-bit) adder. We would augment
the circuit with a signal to initially clear or set the flip-flop
prior to starting the addition.]
4. Draw a 4-bit register using four D flip-flops with five inputs
(consisting of four data bits and one control signal)
i_3, i_2, i_1, i_0, LOAD
and four outputs (consisting of four data bits)
q_3, q_2, q_1, q_0
Example:
Using the hardware in the figure below, write the RTL description and
the control sequence for the following operation. Remember that only
one value can be on the bus at a time.
.-. +-------------+ incrementer will
.-----------------------| |-->| incrementer |--. always increment
| R1_in +------+ R1_out | | +-------------+ o W_in value on bus
`---o-->| R1 |---o--->| | v
+------+ | | W_out +-------+
.-----------------------| |<--o------------| W |
| R2_in +------+ R2_out | | +-------+
`---o-->| R2 |---o--->| |
+------+ | |-----------------------.
.-----------------------| | |
| R3_in +------+ R3_out | | Y_in +-------+ |
`---o-->| R3 |---o--->| |--o-->| Y | |
+------+ | | +-------+ |
.-----------------------| | | |
| R4_in +------+ R4_out | | v v
`---o-->| R4 |---o--->| | ----- -----
+------+ | | \ \______/ /
| | \ / adder will always
... | | \ adder / add value in Y
| | \__________/ with value on bus
| | |
| | o Z_in
| | v
| | Z_out +-------+
| |<--o---------| Z |
`-' +-------+
bus
R[3] <- R[1] + R[2] + 1
RTL corresponding control sequence
-------------------- ------------------------------
1) W <- R[2] + 1; 1) W_in, R[2]_out; // W_in subsumes the +1
2) Y <- W; 2) Y_in, W_out;
3) Z <- R[1] + Y; 3) Z_in, R[1]_out; // Z_in subsumes the add
4) R[3] <- Z; 4) R[3]_in, Z_out;
5. Using the hardware in the figure above, write the RTL description and
the control sequence for the following operations.
(a) R[2] <- R[1] + 1
(b) R[4] <- R[1] + R[2] + R[3]
------
next time
X. Consider the design of a serial comparator takes two inputs A and B ...
state meaning
00 A==B
01 A**B
11 never reached from stating state of 00
(a) give the state diagram
(b) give the truth table
(c) design a circuit
**