CISC instruction set attributes designed for getting lots of work done from a highly-encoded instruction stream (typically designed in the 1970s before icaches became standard but when control stores were large) simple instructions plus many complex instructions, e.g., * inherent looping behavior, such as polynomial evaluation using a table of coefficients as one instruction in the VAX * multi-step addressing modes, such as memory indirect pre/post- indexed modes in the MC68030, which each required a memory fetch, a shift for scaling, and three additions to produce an effective memory address for the operand consequently, lots of instructions (however, the more complex instructions were not frequently used) variable-length instruction formats, e.g., an add instruction on the VAX could range in length from three bytes to 17 bytes (and the length could only be calculated by sequentially decoding up to three addressing mode bytes) RISC instruction set attributes designed for ease of pipelined implementation (typically designed in the 1980s or later, although similar design principles seen in the 1960's CDC 6600) only implement the high-usage simple instructions (simplifies pipelining and keeps the CPI low) fixed instruction length and simple, fixed-field instruction formats (helps in fetching the next instruction and in decoding) load/store architecture - only loads or stores access memory; simple addressing modes - esp. no indirect addressing (at most one memory operation per instruction) explicit specification of registers or other resources (easy comparison for data dependencies) one result per instruction (reduces number of write ports needed for register file) MIPS (1980s) RISC instruction set; load-store architecture; 32-bit and 64-bit versions; instructions are 32 bits in length 32 integer registers; R0 always zero; R31 loaded with return address by jump and link instruction 32 floating-point registers in single precision; double precision uses register pairs assembly language uses $ to indicate a register operand; destination register listed first; 16-bit immediate field add $3,$2,$1 // R3 <- R1 + R2 addi $2,$1,20 // R2 <- R1 + 20 lw $2,20($1) // R2 <- memory[ R1 + 20 ] (word length op) lui $1,20 // upper 16 bits of R1 <- 20 no condition codes beq $1,$2,target // go to target if R1==R2 slt $5,$3,$4 // set R5 to 1 if R3 < R4 beq $5,$0,target // go to target if R5==0 SPARC (1980s) RISC instruction set; load-store architecture; 32-bit and 64-bit versions; instructions are 32 bits in length 32 integer registers; windowed with four 8-register groups (global, input, local, and output - with input and output overlapped for procedure calls); %g0/R0 always zero 32 floating-point registers in single precision; double precision uses register pairs assembly language uses % to indicate a register operand; destination register listed last; 13-bit immediate field add %l1,%l2,%l3 // l3 <- l1 + l2 add %o0,20,%o1 // o1 <- o0 + 20 ld [%o1+20],%i2 // i2 <- memory[ o1 + 20 ] (word length op) sethi 20,%g1 // upper 22 bits of g1 <- 20 four condition codes (NVZC) cmp %l3,%l4 blt target // go to target if l3 < l4 DEC PDP-11 (1970s; led to VAX instruction set in 1980s) CISC-like instruction set; general register architecture; most instructions are two-address format and can have register or memory operands; 16-bit words; instructions are variable length 8 integer registers; R6 is stack pointer; R7 is program counter floating-point was an instruction set extension; one version used a stack of memory locations to hold floating-point operands and results 8 addressing modes (with special-casing when used with R7), including autoincrement (post) and autodecrement (pre) assembly language lists source1 first, with source2/destination listed second; # used to mark immediate value; suffix of 'b' on opcode indicates a byte operation add r1,r2 // r2 <- r1 + r2 add (r1),r2 // r2 <- memory[r1] + r2 add (r1),(r2) // memory[r2] <- memory[r1] + memory[r2] add (r1),4(r2) // memory[r2+4] <- memory[r1] + memory[r2+4] sub r1,r2 // r2 <- r2 - r1 (source1 is subtrahend) add #4,r3 // r3 <- 4 + r3 mov (r0)+,(r1)+ // memory[r1] <- memory[r0] (word wide transfer); // r0 <- r0 + 2; r1 <- r1 + 2 movb (r2)+,(r3)+ // memory[r3] <- memory[r2] (byte wide transfer); // r2 <- r2 + 1; r3 <- r3 + 1 mov -(r4),(r5)+ // r4 <- r4 - 2; memory[r5] <- memory[r4] // (word wide transfer); r5 < r5 + 2; four condition codes (NVZC) cmp r3,r4 blt target // go to target if r3 < r4 Intel x86 (1970s with many extensions) CISC instruction set; extended accumulator architecture; most instructions are two-address format and can have one memory operand (some string instructions can have two memory operands); 16-bit versions (8086-80286), 32-bit versions (386-Pentiums), as well as 64-bit extensions; instructions are variable length 8 integer registers with vestigial purposes and multiple access lengths, e.g., 32-bit EAX overlays 16-bit AX, which itself can be accessed as 8-bit AH (high byte) or 8-bit AL (low byte) EAX - general-purpose accumulator (holds one operand for integer multiply and divide) EBX - base register (used in addressing modes) ECX - count register (used for loop-branch, shift, and string instructions) EDX - data register (used for integer multiply and divide) ESP - stack pointer EBP - base pointer (used as stack frame pointer) ESI - source index register (used in string instructions) EDI - destination index register (used in string instructions) 16-bit and 32-bit architecture versions have floating-point as a stack-based architecture; AMD 64-bit extensions have a general- register architecture multiple addressing modes (depends on architecture version) MASM assembly language lists source2/destination first, with source1 listed second; AT&T-style assembly language reverses order, uses operand length specifiers as suffixes on opcodes, uses % to mark registers, and uses $ to mark immediates mov eax,dword[ebx+ecx*4+loc] // MASM-style; EAX<-memory[loc+EBX+4*ECX] movl loc(%ebx,%ecx,4),%eax // AT&T-style for same instruction // ("dword" and 'l' suffix are used, // respectively, to indicate 32 bits) addl $8,%eax // AT&T-style; EAX <- EAX + 8 addw $8,%ax // AX <- AX + 8 addb $8,%al // AL <- AL + 8 flags register cmp %eax,%ebx jlt target // go to target if EAX < EBX Intel Itanium (1990s) EPIC instruction set; RISC-like instructions arranged into fixed- length (128-bit), three-instruction bundles; 64-bit operations 128 integer registers; windowed somewhat like SPARC 64 one-bit predicate registers; used in branching 128 floating-point registers dedicated support for software-controlled parallelism - predicated instructions to reduce the number of branches - rotating register support for software pipelining; lower 48 of the predicate registers and lower 96 of the integer registers rotate - advance loads to allow the compiler to move a load above a store when alias analysis is incomplete - speculative loads to allow the compiler to move a load above a branch assembly language uses ";;" to mark groups of independent instructions; optionally the programmer or compiler can completely specify bundle types with template and "{"/"}"; uses "=" to visually indicate that destination is listed first add r15 = 44, r0 // r15 <- r0 + 44 ld4 r15 = [r32] // r15 <- memory[r32] // (4-byte-wide transfer) ;; // ;; - load must be done before store st4 [r32] = r14 // memory[r32] <- r14 cmp.eq p1,p2 = r3,r4 // p1 <- (r3==r4); p2 <- ~p1 ;; // ;; - predicates must be set before use (p1) add r5 = 1, r5 // r5 incr if r3==r4 (p2) add r6 = 1, r6 // r6 incr if r3!=r4 other notable instruction sets Burroughs B5500 (1960s) - stack architecture CDC 6600 (1960s) - early RISC-like architecture IBM S/360 (1960s) - general register architecture; dominant mainframe architecture; extensions through today, including 64-bit zSeries Cray-1 (1970s) - vector-register supercomputer architecture DEC VAX (late 1970s) - common CISC example IBM 801 (late 1970s/1980s) - RISC ARM (1980s) - RISC with predicated instructions Motorola 68000 (1980s) - 32-bit microprocessor with many PDP-11-like features DEC Alpha (1990s) - esp. elegant RISC (e.g., no delayed branches) IBM POWER (early 1990s) - "Performance Optimized With Enhanced RISC" IBM PowerPC (1990s) - derivative of POWER