CPSC 330 - Spring 2005
Homework 3
Due by 4:00 on Friday, February 4
Purpose:
(1) work with the execution time equation, CPI, and MIPS
(2) work with SRC instructions and with abstract RTN statements
Note:
For main memory size, interpret K, M, and G as powers of two.
Otherwise, interpret K, M, and G as powers of ten.
Example:
Find the execution time for a program that executes 30 million instructions
on a processor with an avg. CPI of 2.0 and a clock cycle time of 33.3 nsec.
What is the MIPS value?
exec. time = IC * CPI * CCT = 30M insts. * 2 cycles/inst * 33.3 nsec/cycle
= 1.998 seconds = 2 seconds (rounded)
MIPS = insts./ (execution time * 10**6) = 30M insts. / 2*10**6 seconds
= 15 MIPS
1. (a) What is the execution time for a program that executes 10 billion
instructions on a processor with an avg. CPI of 5.0 and a clock rate
of 2 GHz?
(b) What is the MIPS value?
Example:
For the following instruction set workload and cycle values, find the
average CPI. If the clock rate is 100 MHz, what is the MIPS value?
type | freq cycles
-------+--------------
alu | 0.5 2
branch | 0.2 6
ld/st | 0.3 6
avg. CPI = (0.5 * 2) + (0.2 * 6) + (0.3 * 6) = 4.0
MIPS = clock rate / (CPI * 10**6) = 100 MHz / 4*10**6 cycles/inst.
= 100 / 4 = 25 MIPS
2. Consider the following instruction set workload and cycle values.
type | freq cycles
-------+--------------
alu | 0.5 1
branch | 0.2 2
ld/st | 0.3 5
(a) What is the average CPI?
(b) If the clock rate is 2.4 GHz, what is the MIPS value?
Example:
Consider the following C language code segment.
sum = 0;
for(i=1; i<4; i++){
sum = sum + i; - body executes for i= 1,2,3
}
In M68000 assembly, this loop can be expressed as:
clr.w d0 // sum is register-allocated as d0
move.w 1,d1 // i is register-allocated as d1
loop:
cmp d1,#4 // compare i to 4
bge exit // exit if i>=4
add.w d1,d0 // d0 = d0 + d1 (68K assembler inst. format: opc src,dst)
inc d1 // d1 = d1 + 1
bra loop // return to top of loop
exit:
3. Give the code for the C language code segment above in SRC assembly
language. Assume all variables are register-allocated.
Example:
Give the abstract RTN for the SPARC sll instruction. Assume the shift count
is given by n := opnd2: (The opnd2 definition is on p. 131.)
sll (:= op=2 ^ op3=37) -> r[rd]<31..0> <- r[rs1]<31-n..0> # (n@0):
4. Give the abstract RTN for the SPARC sra instruction. Assume the shift count
is given by n := opnd2: (Hint: Consider the RTN of SRC shifts on p. 66.)