Intel P6

Background Material on the Intel P6 (through 2014)

Intel History / Background

Intel logo

Intel Corporate Timeline (see also the Intel Corporate Archives)
Intel Microprocessor Hall of Fame
S.P. Morse, B.W. Ravenel, S. Mazor, and W.B. Pohlman, "Intel Microprocessors -- 8008 to 8086," IEEE Computer, October 1980, pp. 42-60
selected x86 microprocessor introduction dates
- November 1971 - 4004 (400 KHz)
- April 1972 - 8008 (500-800 KHz)
- April 1974 - 8080 (2 MHz)
- March 1976 - 8085 (5 MHz)
- June 1978 - 8086 (5-10 MHz)
- June 1979 - 8088 (5-8 MHz) used in IBM PC
- January 1982 - 80186 (used mostly in controller applications)
- February 1982 - 80286 (6-12 MHz)
- October 1985 - 386 DX (16-33 MHz)
- April 1989 - 486 DX (25-50 MHz)
- March 1993 - Pentium (66 MHz, 60 MHz)
- November 1995 - Pentium Pro (150-200 MHz)
- May 1997 - Pentium II (233-300 MHz)
- February 1999 - Pentium III (450-500 MHz)
- November 2000 - Pentium 4 ("Willamette", 1.4-1.5 GHz)
- March 2003 - Pentium M ("Banias", 900 MHz - 1.6 GHz)
- February 2004 - Pentium 4 ("Prescott", 90nm, 2.8-3.40 GHz)
- April 2005 Pentium Extreme Edition ("Smithfield", dual-core Pentium 4, 3.2 GHz)
- January 2006 - Core Duo ("Yonah", dual core Pentium M, shared L2, 1.5-2.17 GHz)
- June 2006 - Core 2 ("Conroe", 1.87-2.93 GHz)
- November 2008 - i7 ("Bloomfield", 2.67-3.2 GHz)
selected other Intel microprocessor introduction dates
- January 1976 - 8048 (embedded control processor)
- January 1980 - 8051 (embedded control processor)
- January 1981 - 432 (object-oriented)
- February 1989 - i860 (LIW)
- September 1989 - i960 (superscalar RISC series)
- October 1998 - SA-1100 and SA-1101 (StrongARM processors)
- September 1999 - IXP 1200 (network processor)
- September 2000 - 80200 (XScale processor)
- May 2001 - Itanium (EPIC, "Merced", 733-800 MHz)
- July 2002 - Itanium 2 ("McKinley", 900 MHz - 1 GHz)
- March 2008 - Atom ("Silverthorne", 800 MHz - 1.867 GHz)
486 case study
Pentium die layout (gif)
Pentium case study
Robert Hof "Inside Intel," Business Week, June 1, 1992.
Wikipedia articles
- Intel
- 4-bit: 4004, 4040
- 8-bit: 8008, 8080, 8085
- 16-bit: 8086, 8088, 80186, 80188
- segments: 80286
- 32-bit: x86, IA-32, 80386, 80486
- P5: Pentium
- P6: Pentium Pro, Pentium II, Pentium III, Pentium M
- NetBurst: Pentium 4, Pentium D
- Pentium Extreme Edition, Xeon
- Core, Core 2, Core microarchitecture
- Nehalem microarchitecture (see esp. the chart of codenames)
- Sandy Bridge microarchitecture (see esp. the chart of codenames)
- 64-bit extensions to x86: x86-64 (EM64T)
- IA-64, Itanium, Itanium 2
- other Intel processors: iAPX 432, i860, i960, XScale

Intel P6 -- Pentium Pro / Pentium II / Pentium III

P6 chip showing two dies

goals
- performance was primary goal - twice the Pentium
- schedule - planned for end of 1993 (slipped by a year)
- target die size - 10M transistors in 0.6 micron technology (delivered 5.5M transistors)
- power dissipation budget
- clock frequency target - 100 MHz (delivered 150 MHz and 200 MHz)
design cycle
- started in 1990
- microarchitecture and performance model - 1 year
- behavioral and structural models - 3/4 year
- logic design, ciruit design, and layout - 1 3/4 years
- first silicon in December 1994
  - boot and run DOS - 2 days after first silicon
  - boot and run WinNT in multiprocessor mode - 12 weeks after first silicon (stepping A1)
- production tape-out (release to manufacturing) in August 1995
- offered for sale in November 1995
chip architects were Bob Colwell (chief), Glenn Hinton (senior), Dave Papworth (senior), Michael Fetterman, and Andy Glew
team structure (see The Pentium Chronicles, Figure 2.3, p. 36)
- architects (including microcoding and multiprocessing, see pp. 38-39)
- design
- pre-silicon validation (incorporated into architecture team, see pp. 36-37)
- post-silicon validation
- chip set
- marketing
proliferation
- Pentium Pro - 1995, P6 core
- Pentium II - 1997, P6 core + MMX
- Pentium III - 1999, P6 core + MMX + SSE

characteristics

decoupled microarchitecture: translates x86 instructions into internal uops (micro-operations)

pipeline organization

8-stage in-order pipeline - decodes up to three x86 insts. per cycle, but only one can be complex (e.g., memory-to-reg); each x86 inst. is translated into one or more fixed-length uops; uops are placed into 20-entry reservation station
3-stage out-of-order core - issue up to four uops per cycle, results from completed uops written to 40-entry reorder buffer

3-stage retirement pipeline - retire up to three uops per cycle

               front-end                execution core      back-end        
               ---------                --------------      --------
                                                            
               I1 - next IP
      1   .--> I2 - Icache 1
      2   |    I3 - Icache 2 / ILD
      3   |    I4 - Decode 1 / rotate
      4   |    I5 - Decode 2
      5   |    I6 - Decode 3
      6   |    I7 - Register rename
      7   |    I8 - RS write
      8   |                             O1 - RS schedule
      9   |                             O2 - RS dispatch
     10   `---- branch mispredict ----- O3 - execute
                                                            R1 - Retire 1
                                                            R2 - Retire 2
                                                            R3 - RRF write

branch prediction
- 512-entry, 4-way set-associative BTB using PAs prediction scheme (4-bit per-address BHSRs stored in the BTB entries index into one of four 16-entry PHTs); correct prediction of untaken yields no penalty, correct prediction of taken yields one cycle stall, misprediction yields 10-15 cycle penalty
- decoder "shortstop" predicts branch based on its displacement when it is not in BTB; untaken forward branches yield no penalty, taken backward branches yield 5-6 cycle penalty, misprediction yields 10-15 cycle penalty
register-renaming for three uops per cycle to avoid WAR and WAW dependencies
uop scheduling takes into account forwarding paths
on-chip L1 and L2 caches; L1 is pseudo-dual-ported 8 KB (4 interleaved banks) with 2-cycle hit; L2 is 256 KB, 512 KB, or 1 MB, runs at processor clock speed, L1 miss/L2 hit is 6 cycles

The Pentium® Pro Processor Fact Sheet:

Clock speed (MHz)	166	180	200	200
Bus Speed (MHz)	66	60	66	66
L2 Cache	512K	256K	256K	512K
Manuf. Process	0.35 micron	0.35 micron	0.35 micron	0.35 micron
Die Size	552 mils/side	552 mils/side	552 mils/side	552 mils/side
CPU Voltage	3.3V	3.3V	3.3V	3.3V
Maximum Current	9.4A	10.1A	11.2A	12.4A
Power (Watts)	27.5 typ; 35.0 max	25.3 typ; 31.7 max	28.1 typ; 35.0 max	32.6 typ; 37.9 max
Performance*	7.22 SPECint95 5.84 SPECfp95	7.28 SPECint95 5.59 SPECfp95	8.20 SPECint95 6.21 SPECfp95	8.58 SPECint95 6.48 SPECfp95

Other data, for all Pentium Pro processors:
Internal Bus Width:	300 bits
External Bus Width:	64 bits front side; 64 bits to L2 cache
Virtual Addr. Space:	64 Terabytes
Physical Addr. Space:	64 Gigabytes
Math Co-Processor Support:	Built-in
Dynamic Execution:	Yes
Superscalar:	Yes
CPU Transistors:	~5.5 million
Package Size:	2.46 inches x 2.66 inches
Package Type:	Dual Cavity PGA, 387 pins
L1 Cache:	8K I + 8K D
First-Level Cache Controller:	Built-in
Second-Level Cache Controller:	Built-in

L2 Cache details:
Cache size:	256K	512K
Die size:	671x467 mils (202 sq. mm)	580x650 mils (242 sq. mm)
Process:	0.6 micron	0.35 micron
Transistors:	15.5 million	31 million
Speed:	Core speed	Core speed

(from www.intel.com)

R. Colwell, et al., "Intel's P6 Microarchitecture," chapter 7 in Shen and Lipasti, Modern Processor Design
P6 manuals and CR-ROM contents from x86.org
- The P6 Architecture: Background for Developers (pdf)
- Dynamic Execution Explanation (pdf)
- A Tour of the P6 Microarchitecture (pdf)
- P6 Optimization Guide (pdf)
- Intel P6 Microarchitecture Tuning Guide (pdf)
D. Papworth, "Tuning the Pentium Pro Microarchitecture," Computer, April 1996, pp. 8-15.
- goal was to achieve 1.5x to 2.0x the performance of the Pentium
- Intel doesn't control x86 software applications or compilers, so out-of-order execution and register renaming were seen as being required to reach the performance goal
- the first effort planning for the P6
  - 100 MHz on 0.6 micron technology
  - 10-stage pipeline
  - four-instruction decoder (4-2-2-2 uops capable)
  - four uops per cycle renaming and retiring
  - dual 32K L1 caches (I+D)
  - two load/store ports to dcache
  - 10 M transistors
- the P6 they actually built
  - 150 MHz on 0.6 micron technology
  - 14-stage pipeline
  - three-instruction decoder (4-1-1 uops capable)
  - three uops per cycle renaming and retiring
  - dual 8K L1 caches (I+D)
  - one load port and one store port to dcache
  - 5.5 M transistors
- an optical shrink to 0.35 micron process technology ran at 200 MHz and was also available at the announcement in Nov. 1995
  - the classic Pentium, a.k.a. P5, was available at various clock speeds in the range 60-133 MHz at the time
  - the fastest chip at the time was the 300 MHz Alpha 21164
  - the 200 MHz Pentium Pro "caught the industry by surprise and vaulted the x86 vendor into the performance lead" on SPEC95 (Microprocessor Report, July 8, 1996) [DEC immediately responded with a 333 MHz version of the 21264 and within a year had a 500 MHz version]
D.T. Marr, S. Natarajan, S. Thakkar, and R. Zucker, "Multiprocessor Validation of the Pentium Pro," IEEE Computer, November 1996, pp. 47-53.
D. Bhandarkar and J. Ding, "Performance Characterization of the Pentium Pro Processor," HPCA-3, February 1997, pp. 288-297.
A. Carbine and D. Feltham, "Pentium Pro Processor Design for Test and Debug," International Test Conference, November 1997, pp. 294-303.

for comparison and context, see Robert Yung's PhD dissertation, "Evaluation of a Commercial Microprocessor," UC Berkeley, SMLI TR-98-65, June 1998, 233pp, which describes the design decisions for the UltraSPARC microprocessor. Chapter 3 of his dissertation discusses design principles and pitfalls, and Chapter 6 discusses lessons learned with respect to design methodologies, business decisions, and technology considerations.

See also these figures and tables that include the P6 and other contemporary designs.

point of comparison figure or table number page in Yung

relative performance Figure 1-1 5

clock frequency Figure 1-2 6

transistor count Figure 1-3 7

core only Figure 1-4 8

costs Table 2-7 44

general comparison Table 2-10 52

integer perf. vs. clock Figure 2-4 60

fp perf. vs. clock Figure 2-5 60

integer performance Figure 2-6 62

fp performance Figure 2-7 63

Things CPU Architects Need To Think About (abstract), Stanford University Computer Systems Laboratory, EE380 Colloquium Series, Feb. 18, 2004. [broken link]
Bob Colwell and Konrad Lai, "Eternal Vigilance is the Price of Performance," ISCA Performance Validation Workshop presentation, 1995 (ppt)
Dave Papworth and Bob Colwell, "Avoiding Accidental Performance Decisions," PAID '97 presentation (ppt)
Bob Colwell, "What Computer Architects Really Do (Or Should)," ISCA '05 presentation (ppt)
Kris Mamula, "Chips Ahoy," Pitt Magazine, Sept. 2001 (profile of Bob Colwell)
Pentium III die layout (tiff)
Jagannath Keshava and Vladimir Pentkovski, "Pentium III Processor Implementation Tradeoffs," Intel Technology Journal, vol. 2, qtr. 2, 1999.
many patents - one example is US Patent 5,574,942, "Hybrid execution unit for complex microprocessor," R. Colwell, D. Papworth, M. Fetterman, A. Glew, G. Hinton, S. Coward, and G. Chen

point of comparison	figure or table number	page in Yung
relative performance	Figure 1-1	5
clock frequency	Figure 1-2	6
transistor count	Figure 1-3	7
core only	Figure 1-4	8
costs	Table 2-7	44
general comparison	Table 2-10	52
integer perf. vs. clock	Figure 2-4	60
fp perf. vs. clock	Figure 2-5	60
integer performance	Figure 2-6	62
fp performance	Figure 2-7	63

Intel Pentium 4 (2000)

revised microarchitecture, called NetBurst, using a trace cache
SSE2 (2000) and SSE3 (2004)
first generation parts codenamed Willamette and Northwood
second generation parts codenamed Prescott and Cedar Mill
second generation (Prescott) had an even deeper pipeline (said to be 31 stages versus 20 stages in Willamette), but power dissipation problems eventually led to Intel dropping this approach
Quote from Making IT Better: Expanding Information Technology Research to Meet Society's Needs, Computer Science and Telecommunications Board (CSTB), 2000, footnote 3, pp. 136-137
In the original Pentium Pro, which had about 5.5 million transistors in the central processing unit, Intel found and corrected 1,200 design errors prior to production; in its forthcoming Willamette processor, which has 30 million transistors in the central processing unit, engineers have found and corrected 8,500 design flaws (data from Robert Colwell, Intel, personal communication, March 14, 2000).
Pentium 4 die layout (jpg)
Pentium 4 case study
Doug Carmean, Pentium 4 Microarchitecture slides (pdf)
floating-point optimization across several Intel generations
Bob Bentley, "Validating the Intel Pentium 4 Microprocessor," (pdf) DAC 2001
Bob Bentley, Validating a Modern Microprocessor slides (ppt) CAV 2001

Pentium M (2003)

revised P6 core (extension of Pentium III mobile), done in Israel, also known by codenames of Banias and Dothan
micro-fusion: combines uops from one instruction into a single complex uop that can be tracked by the out-of-order hardware as a single entity (e.g., load and execute, store-address and store-data)
Simcha Gochman, et al., "The Intel Pentium M Processor: Microarchitecture and Performance," Intel Technology Journal, vol. 7, no. 2, 2003.
Intel Pentium M Processor Power Estimation, Budgeting, Optimization and Validation (pdf)

Intel Core (2006)

wikipedia article on Core microarchitecture
four decoders (4-1-1-1)
macro-fusion: combines two x86 instructions into one uop (e.g., CMP/Jcc for CF and ZF flags)
retirement limit of four uops per cycle
SSSE3 and SSE4.1
Conroe: Grandson of Pentium III, Nephew of NetBurst?
Pat Gelsinger, "Into the Core ..." (abstract), Stanford University Computer Systems Laboratory, EE380 Colloquium Series, June 7, 2006 [available on the web, Windows Media, 75 mins.]
white paper on new core (pdf)
special issue of Intel Tech Journal
T.K. Prakash, "Performance Analysis of Intel Core 2 Duo Processor," MS thesis, LSU, 2007 [see the IPC and instruction distribution charts]

Intel Nehalem (2008)

David Kanter, Inside Nehalem: Intel's Future Processor and System, Real World Technologies, April 2, 2008
wikipedia article on Nehalem microarchitecture
macro fusion for 64-bit instructions, hyper-threading (SMT)
QPI (quick path interface)
SSE4.2
Glenn Hinton, "Intel's Nehalem Microarchitecture" (abstract), Stanford University Computer Systems Laboratory, EE380 Colloquium Series, February 17, 2010 [available on the web, Windows Media, 75 mins.]
shrink named Westmere

Intel Sandy Bridge (2011)

David Kanter, Intel's Sandy Bridge Microarchitecture, Real World Technologies, Sept. 25, 2010
wikipedia article on Sandy Bridge microarchitecture
Andy Glew writing in comp.arch, Dec. 8, 2010:

Sandy Bridge is what P6 version 2.0 should have been.
It's the first new OOO core from Intel, designed by people who actually believed in OOO. Pentium 4 was designed by people who really did not want to be doing OOO, but were forced to because the simulators showed what they really wanted to build did not work.
Although Sandy Bridge was marketed as a P6 family core, it really is a step beyond.
on-chip memory controller and integrated graphics, uop cache, AVX vector instruction set extension
shrink named Ivy Bridge, includes new random number generator
Intel 64 and IA-32 Architectures Optimization Reference Manual, April 2012 (includes Sandy Bridge overview)

Intel Haswell (2013)

Per Hammarlund, 4th Generation Intel Core Processor, codenamed Haswell, HotChips-25, 2013
David Kanter, Intel's Haswell CPU Microarchitecture, Real World Technologies, Nov. 13, 2012
wikipedia article on Haswell microarchitecture
AVX2, FMA3, gather, bit manipulation, and TSX (note TSX disabled by microcode update on early chips because of bug)
Intel Architecture Instruction Set Extensions Programming Reference, August 2012 (includes AVX and TSX extensions)
shrink to be named Broadwell, should include new arbitrary precision integer operations

Intel Skylake (due 2015)

wikipedia article on Skylake microarchitecture

Discussion questions for The Pentium Chronicles