cycle diagram | 111111 ........................|123456789012345 0: la r1,r0,3 |FDAMW . . 4: la r2,r0,4 | FDAMW . . 8: add r1,r1,r1 | F--DAMW. . 12: add r2,r2,r2 | F--DAMW . 16: add r3,r1,r2 | . F---DAMW. 20: stop | . F---DAMW cycle 1: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 0 | PC_in: 4 - - - - - - - +-----+ 1 IF: IR2_in: la r1,r0,3 PC2_in: 4 +------------------+ +-----+ IF/ID:- - - - IR2| empty | - -PC2| 0 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: | | +---------------------------------------------+ IR3_in: empty X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| empty |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: empty Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| empty |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: empty Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| empty |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 0 0 0 0 0 cycle 2: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 4 | PC_in: 8 - - - - - - - +-----+ 1 IF: IR2_in: la r2,r0,4 PC2_in: 8 +------------------+ +-----+ IF/ID:- - - - IR2| la r1,r0,3 | - -PC2| 4 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: | | +---------------------------------------------+ IR3_in: la r1 X3_in: 0 Y3_in: 3 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| empty |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: empty Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| empty |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: empty Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| empty |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 1 0 0 0 0 0 0 cycle 3: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 8 | PC_in: 12 - - - - - - - +-----+ 1 IF: IR2_in: add r1,r1,r1 PC2_in: 12 +------------------+ +-----+ IF/ID:- - - - IR2| la r2,r0,4 | - -PC2| 8 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: | | +---------------------------------------------+ IR3_in: la r2 X3_in: 0 Y3_in: 4 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| la r1 |- - - - - - X3| 0 |- - -Y3| 3 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: `----------------->alufn: add IR4_in: la r1 Z4_in: 3 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| empty |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: empty Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| empty |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 1 1 0 0 0 0 0 cycle 4: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 12 | PC_in: 16 - - - - - - - +-----+ 1 IF: IR2_in: add r2,r2,r2 PC2_in: 16 +------------------+ +-----+ IF/ID:- - - - IR2| add r1,r1,r1 | - -PC2| 12 | - - - - - - - - - - - - - +------------------+ +-----+ ********* +---------------------------------------------+ 2 ID: * STALL * | | ********* +---------------------------------------------+ IR3_in: X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| la r2 |- - - - - - X3| 0 |- - -Y3| 4 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: `----------------->alufn: add IR4_in: la r2 Z4_in: 4 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| la r1 |- - - - - - - - - - Z4| 3 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: la r1 Z5_in: 3 +-----------+ +----+ MEM/WB: - - - IR5| empty |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 1 1 0 0 0 0 0 cycle 5: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 12 | PC_in: 16 - - - - - - - +-----+ 1 IF: IR2_in: add r2,r2,r2 PC2_in: 16 +------------------+ +-----+ IF/ID:- - - - IR2| add r1,r1,r1 | - -PC2| 12 | - - - - - - - - - - - - - +------------------+ +-----+ ********* +---------------------------------------------+ 2 ID: * STALL * write | a3: r1 R3: 3 | ********* +---------------------------------------------+ IR3_in: X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| la r2 |- - - - - - - - - - Z4| 4 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: la r2 Z5_in: 4 +-----------+ +----+ MEM/WB: - - - IR5| la r1 |- - - - - - - - - - Z5| 3 |- - - - - - - - - - +-----------+ +----+ 5 WB: `-----> write r1 register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 1 0 0 0 0 0 cycle 6: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 12 | PC_in: 16 - - - - - - - +-----+ 1 IF: IR2_in: add r2,r2,r2 PC2_in: 16 +------------------+ +-----+ IF/ID:- - - - IR2| add r1,r1,r1 | - -PC2| 12 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: read & write | a1: r1 R1: 3 a2: r1 R2: 3 a3: r2 R3: 4 | +---------------------------------------------+ IR3_in: add r1 X3_in: 3 Y3_in: 3 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| la r2 |- - - - - - - - - - Z5| 4 |- - - - - - - - - - +-----------+ +----+ 5 WB: `-----> write r2 register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 3 | 4 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 1 0 0 0 0 0 0 cycle 7: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 16 | PC_in: 20 - - - - - - - +-----+ 1 IF: IR2_in: add r3,r1,r2 PC2_in: 20 +------------------+ +-----+ IF/ID:- - - - IR2| add r2,r2,r2 | - -PC2| 16 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: read | a1: r2 R1: 4 a2: r2 R2: 4 | +---------------------------------------------+ IR3_in: add r2 X3_in: 4 Y3_in: 4 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| add r1 |- - - - - - X3| 3 |- - -Y3| 3 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: `----------------->alufn: add IR4_in: add r1 Z4_in: 6 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 3 | 4 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 1 1 0 0 0 0 0 cycle 8: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 20 | PC_in: 24 - - - - - - - +-----+ 1 IF: IR2_in: stop PC2_in: 24 +------------------+ +-----+ IF/ID:- - - - IR2| add r3,r1,r2 | - -PC2| 20 | - - - - - - - - - - - - - +------------------+ +-----+ ********* +---------------------------------------------+ 2 ID: * STALL * | | ********* +---------------------------------------------+ IR3_in: X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| add r2 |- - - - - - X3| 4 |- - -Y3| 4 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: `----------------->alufn: add IR4_in: add r2 Z4_in: 8 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| add r1 |- - - - - - - - - - Z4| 6 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: add r1 Z5_in: 6 +-----------+ +----+ MEM/WB: - - - IR5| |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 3 | 4 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 1 1 0 0 0 0 0 cycle 9: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 20 | PC_in: 24 - - - - - - - +-----+ 1 IF: IR2_in: stop PC2_in: 24 +------------------+ +-----+ IF/ID:- - - - IR2| add r3,r1,r2 | - -PC2| 20 | - - - - - - - - - - - - - +------------------+ +-----+ ********* +---------------------------------------------+ 2 ID: * STALL * write | a3: r1 R3: 6 | ********* +---------------------------------------------+ IR3_in: X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| add r2 |- - - - - - - - - - Z4| 8 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: add r2 Z5_in: 8 +-----------+ +----+ MEM/WB: - - - IR5| add r1 |- - - - - - - - - - Z5| 6 |- - - - - - - - - - +-----------+ +----+ 5 WB: `-----> write r1 register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 6 | 4 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 1 0 0 0 0 0 cycle 10: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 20 | PC_in: 24 - - - - - - - +-----+ 1 IF: IR2_in: stop PC2_in: 24 +------------------+ +-----+ IF/ID:- - - - IR2| add r3,r1,r2 | - -PC2| 20 | - - - - - - - - - - - - - +------------------+ +-----+ ********* +---------------------------------------------+ 2 ID: * STALL * write | a3: r2 R3: 8 | ********* +---------------------------------------------+ IR3_in: X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| add r2 |- - - - - - - - - - Z5| 8 |- - - - - - - - - - +-----------+ +----+ 5 WB: `-----> write r2 register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 6 | 8 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 0 0 0 0 0 cycle 11: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 20 | PC_in: 24 - - - - - - - +-----+ 1 IF: IR2_in: stop PC2_in: 24 +------------------+ +-----+ IF/ID:- - - - IR2| add r3,r1,r2 | - -PC2| 20 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: read | a1: r1 R1: 6 a2: r2 R2: 8 | +---------------------------------------------+ IR3_in: add r3 X3_in: 6 Y3_in: 8 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 6 | 8 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 1 0 0 0 0 cycle 12: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 24 | PC_in: 28 - - - - - - - +-----+ 1 IF: IR2_in: empty PC2_in: 28 +------------------+ +-----+ IF/ID:- - - - IR2| stop | - -PC2| 24 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: | | +---------------------------------------------+ IR3_in: stop X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| add r3 |- - - - - - X3| 6 |- - -Y3| 8 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: `----------------->alufn: add IR4_in: add r3 Z4_in: 14 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 6 | 8 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 1 0 0 0 0 cycle 13: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 28 | PC_in: 32 - - - - - - - +-----+ 1 IF: IR2_in: empty PC2_in: 32 +------------------+ +-----+ IF/ID:- - - - IR2| empty | - -PC2| 28 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: | | +---------------------------------------------+ IR3_in: empty X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| stop |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: stop Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| add r3 |- - - - - - - - - - Z4| 14 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: add r3 Z5_in: 14 +-----------+ +----+ MEM/WB: - - - IR5| |- - - - - - - - - - Z5| 0 |- - - - - - - - - - +-----------+ +----+ 5 WB: register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 6 | 8 | 0 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 1 0 0 0 0 cycle 14: +-----+ - /IF:- - - - - - - - - - - - - - - - - - PC| 32 | PC_in: 36 - - - - - - - +-----+ 1 IF: IR2_in: empty PC2_in: 36 +------------------+ +-----+ IF/ID:- - - - IR2| empty | - -PC2| 32 | - - - - - - - - - - - - - +------------------+ +-----+ +---------------------------------------------+ 2 ID: write | a3: r3 R3: 14 | +---------------------------------------------+ IR3_in: empty X3_in: 0 Y3_in: 0 MD3_in: 0 +-----------+ +----+ +----+ +----+ ID/ALU: - - - IR3| empty |- - - - - - X3| 0 |- - -Y3| 0 | - - MD3| 0 | +-----------+ +----+ +----+ +----+ 3 ALU: IR4_in: empty Z4_in: 0 MD4_in: 0 +-----------+ +----+ +----+ ALU/MEM: - - -IR4| stop |- - - - - - - - - - Z4| 0 |- - - - - MD4| 0 | +-----------+ +----+ +----+ 4 MEM: IR5_in: stop Z5_in: 0 +-----------+ +----+ MEM/WB: - - - IR5| add r3 |- - - - - - - - - - Z5| 14 |- - - - - - - - - - +-----------+ +----+ 5 WB: `-----> write r3 register r0 r1 r2 r3 r4 r5 r6 r7 --------+-----+-----+-----+-----+-----+-----+-----+-----+ contains| 0 | 6 | 8 | 14 | 0 | 0 | 0 | 0 | --------+-----+-----+-----+-----+-----+-----+-----+-----+ busy bit 0 0 0 0 0 0 0 0