CPSC 330 - Fall 2005 Program 2 Due by midnight on Monday, October 10 Turn in using "handin.330.1 2 ". Write a program that simulates the simple microprogrammed CPU found in http://www.cs.clemson.edu/~mark/uprog.html There should be: 1024 x 12-bit main memory 10-bit registers: PC, MAR 12-bit registers: IR, MDR, ACC, TMP and 16 x 20-bit control store 8-bit CSAR 20-bit CSIR The instruction format is a 2-bit opcode followed by a 10-bit address. The microinstruction format follows what is given on the web page. The instruction set is: load -- opcode = 00 -- acc <- mem[addr] add -- opcode = 01 -- acc <- acc + mem[addr] store -- opcode = 10 -- mem[addr] <- acc brz -- opcode = 11 -- if( acc==0 ) pc <- addr Execution starts at address 0, and the instruction brz 1023 (that is, when IR == 0xfff) means halt the simulation. Registers should be initialized to 0, and the control store should be set to the contents given in Figure 4 of the web page. For input, you should read from stdin a list of memory words in hex, ending with a sentinel of -1. For output, you should print the initial contents of the first few words of memory, a cycle-by-cycle trace of control signals, and finally the ending contents of the first few words of memory. The cycle-by-cycle trace should include the contents of all six control and datapath registers, along with the CSAR and CSIR, prior to the execution of the microinstruction for that cycle. The CSIR should be printed bit-by-bit except for the next address field. For the following simple program, the simulator should produce the appended output. (You can change the output format, but at least the same amount of information should be printed.) test program: load a add b brz zero add b brz zero add b zero: store c brz 1023 a: .word 2 b: .word -1 c: .word 5 input (after hand assembly): 8 409 c06 409 c06 409 80a fff 2 fff 5 -1 simulator output: start of simulation of simple cpu memory: 8 409 c06 409 c06 409 80a fff 2 fff 5 0 0 0 0 0 0 0 0 0 cycle PC IR MAR MDR ACC TMP CSAR CSIR --------------------------------------------------------------- 1: 0 0 0 0 0 0 0 00000100010000020 MAR_in PC_out 2: 0 0 0 0 0 0 2 00000000001100030 pc_incr read 3: 1 0 0 8 0 0 3 00010001000000040 IR_in MDR_out 4: 1 8 0 8 0 0 4 00000000000000100 br_table 5: 1 8 0 8 0 0 5 00001100000000060 IR_out MAR_in 6: 1 8 8 8 0 0 6 00000000000100070 read 7: 1 8 8 2 0 0 7 10000001000000000 ACC_in MDR_out --------------------------------------------------------------- 8: 1 8 8 2 2 0 0 00000100010000020 MAR_in PC_out 9: 1 8 1 2 2 0 2 00000000001100030 pc_incr read 10: 2 8 1 409 2 0 3 00010001000000040 IR_in MDR_out 11: 2 409 1 409 2 0 4 00000000000000100 br_table 12: 2 409 1 409 2 0 8 00001100000000090 IR_out MAR_in 13: 2 409 9 409 2 0 9 000000000001000a0 read 14: 2 409 9 fff 2 0 a 011000000000000b0 ACC_out alu_add 15: 2 409 9 fff 2 1 b 10000000000010000 ACC_in TMP_out --------------------------------------------------------------- 16: 2 409 9 fff 1 1 0 00000100010000020 MAR_in PC_out 17: 2 409 2 fff 1 1 2 00000000001100030 pc_incr read 18: 3 409 2 c06 1 1 3 00010001000000040 IR_in MDR_out 19: 3 c06 2 c06 1 1 4 00000000000000100 br_table 20: 3 c06 2 c06 1 1 f 00000000000000001 or_addr --------------------------------------------------------------- 21: 3 c06 2 c06 1 1 0 00000100010000020 MAR_in PC_out 22: 3 c06 3 c06 1 1 2 00000000001100030 pc_incr read 23: 4 c06 3 409 1 1 3 00010001000000040 IR_in MDR_out 24: 4 409 3 409 1 1 4 00000000000000100 br_table 25: 4 409 3 409 1 1 8 00001100000000090 IR_out MAR_in 26: 4 409 9 409 1 1 9 000000000001000a0 read 27: 4 409 9 fff 1 1 a 011000000000000b0 ACC_out alu_add 28: 4 409 9 fff 1 0 b 10000000000010000 ACC_in TMP_out --------------------------------------------------------------- 29: 4 409 9 fff 0 0 0 00000100010000020 MAR_in PC_out 30: 4 409 4 fff 0 0 2 00000000001100030 pc_incr read 31: 5 409 4 c06 0 0 3 00010001000000040 IR_in MDR_out 32: 5 c06 4 c06 0 0 4 00000000000000100 br_table 33: 5 c06 4 c06 0 0 f 00000000000000001 or_addr 34: 5 c06 4 c06 0 0 1 00001000100000000 IR_out PC_in --------------------------------------------------------------- 35: 6 c06 4 c06 0 0 0 00000100010000020 MAR_in PC_out 36: 6 c06 6 c06 0 0 2 00000000001100030 pc_incr read 37: 7 c06 6 80a 0 0 3 00010001000000040 IR_in MDR_out 38: 7 80a 6 80a 0 0 4 00000000000000100 br_table 39: 7 80a 6 80a 0 0 c 000011000000000d0 IR_out MAR_in 40: 7 80a a 80a 0 0 d 010000100000000e0 ACC_out MDR_in 41: 7 80a a 0 0 0 e 00000000000001000 write --------------------------------------------------------------- 42: 7 80a a 0 0 0 0 00000100010000020 MAR_in PC_out 43: 7 80a 7 0 0 0 2 00000000001100030 pc_incr read 44: 8 80a 7 fff 0 0 3 00010001000000040 IR_in MDR_out 45: 8 fff 7 fff 0 0 4 00000000000000100 br_table --------------------------------------------------------------- end of simulation memory: 8 409 c06 409 c06 409 80a fff 2 fff 0 0 0 0 0 0 0 0 0 0