CPSC 330 Spring 2005 Program 2 Due by midnight on Friday, March 18. * Choose one or the other program. * Or, you can work together in teams of two and turn in both programs. (Each team member can receive the average of the two program grades, or the team members can elect to be each graded on a different program.) Different teams and individuals not on teams should not discuss the solution to this assignment with each other. For this assignment, you are to write one of two programs that will correspond to the datapath of Figure 2.23 of the text. One program will be a translator that will generate binary control words from abstract RTN; the other program will be a simulator to execute those control words on the data path. abstract RTN file | v .------------. | translator | `------------' | v control word file | v .------------. | simulator | `------------' | v simulator output (time step by time step) You may use any programming language you wish. (Each part is 100 lines or less of code in C - about 2 pages.) They must work on Solaris (Unix) systems using standard I/O (and thus allow I/O redirection). grading: program correctness: 80% test cases and testing log: 20% data path specifics: - based on Figure 2.23 from your textbook - registers w,y,z and r0 through r5 - each register starts the simulation with value 0 - r0 cannot be changed (always contains a zero) translator: You are to read a set of simple RTN expressions from a file and translate them into 16-bit control words, printed as four hex digits. The RTN statements should be structured according to the following simple regular grammar (where 1<=d<=5, 0<=s<=5): rd<-{1|rs}{+1|+rs}*; There should be one statement per line, with no embedded spaces. An input line cannot be longer than 79 characters; and, the last line contains the single keyword "end", which should be translated to 0000. You should check for syntax errors (anything not recognized) and range check the register numbers. (r0 can be a source but not a destination.) A state machine is given on a separate handout. You are to prepare several test cases and show that you have hand-checked that the results are correct. You will be graded on the coverage of your test cases. (Some of these test case should include deliberate errors in order to test your error-checking code.) simulator: You are to read 16-bit control words from an input file. There will be one word per line. Each word will be stored as four ASCII characters, representing the four hex digits of the control word. The last control word will be 0000, representing the end of the control sequence. You are to print the control signal names and to perform the transfers. You must check for one and only one value placed on the bus during each time step. If there is more than one output, stop and exit the simulator after printing an error message. You are to prepare several test cases and show that you have hand-checked that the results are correct. You will be graded on the coverage of your test cases. (Some of these test case should include deliberate errors in order to test your error-checking code.) control word encoding - 8-bit in field, 8-bit out field: in field out field ------------ ------------- 0x80 - w_in 0x80 - w_out note: remember that 0x40 - y_in 0x40 - r0_out w_in means w <- bus + 1 0x20 - z_in 0x20 - z_out z_in means z <- bus + y 0x10 - r1_in 0x10 - r1_out 0x08 - r2_in 0x08 - r2_out so, for example, the control word 0x04 - r3_in 0x04 - r3_out value 0x2004 means z_in,r3_out 0x02 - r4_in 0x02 - r4_out or, in concrete RTN, z <- r3 + y 0x01 - r5_in 0x01 - r5_out Example input and output files ------------------------------ example rtn file contents (input to the translator): r1<-1; r2<-r0; r2<-r1+r1; r3<-1+1+1; end corresponding concrete rtn: (can come from the translator but this is not required -- however, it may be helpful during the early phases of debugging your translator to print these rather than printing the control words; these RTN statements are in one-to-one correspondence with the control words) w <- r0+1 r1 <- w r2 <- r0 y <- r1 z <- r1+y r2 <- z w <- r0+1 w <- w+1 w <- w+1 r3 <- w end corresponding control word file contents (output from the translator, and input to the simulator): 8040 1080 0840 4010 2010 0820 8040 8080 8080 0480 0000 simulator output: step control word | cntl signals | w y z r1 r2 r3 r4 r5 | -------------------+--------------+---------------------------------+ T00: in=80 out=40 | w_in ,r0_out | 1 0 0 0 0 0 0 0 | T01: in=10 out=80 | r1_in,w_out | 1 0 0 1 0 0 0 0 | T02: in=08 out=40 | r2_in,r0_out | 1 0 0 1 0 0 0 0 | T03: in=40 out=10 | y_in ,r1_out | 1 1 0 1 0 0 0 0 | T04: in=20 out=10 | z_in ,r1_out | 1 1 2 1 0 0 0 0 | T05: in=08 out=20 | r2_in,z_out | 1 1 2 1 2 0 0 0 | T06: in=80 out=40 | w_in ,r0_out | 1 1 2 1 2 0 0 0 | T07: in=80 out=80 | w_in ,w_out | 2 1 2 1 2 0 0 0 | T08: in=80 out=80 | w_in ,w_out | 3 1 2 1 2 0 0 0 | T09: in=04 out=80 | r3_in,w_out | 3 1 2 1 2 3 0 0 | -------------------+--------------+---------------------------------+ end example of error checking in translator r<1; *** assignment syntax error in r<1; r0<-1; *** out of range register number r0 r2<-r7; *** out of range register number r7 example of error checking in simulator 8003 0000 step control word | cntl signals | w y z r1 r2 r3 r4 r5 | -------------------+--------------+---------------------------------+ T00: in=80 out=03 | w_in ,r4_out,r5_out *** error - more than one output to bus ***