CPSC 330 - Spring 2007 Homework 3 Due by class time on Monday, March 26 Example: +----------+ +---------------+ +-------------+ | source |--|>-------bus------| combinational |--------| destination | | register | | | logic | .--| register | +----------+ | +---------------+ | +-------------+ R_out R_in |<---propagation---->|<----logic---->|<--setup-->|<--hold-->| | delay for bus delay time time | | | |<----------------minimum clock cycle time----------------->| For clock timing, you find the delay time along the longest active path in a datapath. Delays can typically be separately idenitifed, as done in the diagram above. Then, for example, if each identified component of the delay time is 1 nsec, the minimum clock cycle time would be 4 nsec, and the maximum clock rate would be 250 MHz. 1. Question 7.4 of your textbook, p. 446. Example: see Figure 7.6 in your textbook, p. 421 (for background on the instruction set, see sections 2.4-2.6 in your textbook) 2. Question 7.5 (a,b) of your textbook, p. 446. (a) is ADD #NUM,R1 or ADDI NUM,R1 (b) is ADD NUM,R1 Example: see the answers to Fall 2006 Exam 2 3. Consider the following datapath. (Assume all registers are edge-triggered and thus immune from races.) Control signal names are given near the in and out control points of the registers. Additional control signals include memory signals R, W, and WFMC, and the ALU function selector F. Give the step-by-step RTL and the control signal sequence to fetch and execute a load with post-incremented-index -- LOAD M(X)+ instruction. Assume the instruction has an opcode and address field placed together in a single word and that the memory is word addressable. The actions of the instruction are ACC <- memory[M+X]; // load the accumulator (ACC) from memory, where // the effective address is the address field // from the instruction (M) plus the contents of // the index register (X) X <- X + 1; // post-increment the index register (X) A.bus B.bus _ _ PC.A.in | |--o->+-----+<-o--| | PC.B.in | | | PC | | | PC.A.out | |<-o--+-----+--o->| | PC.B.out | | | | IR.A.in | |--o->+-----+<-o--| | IR.B.in | | | IR | | | IR_addr.A.out | |<-o--+-----+--o->| | IR_addr.B.out | | | | MDR.A.in | |--o->+-----+<-o--| | MDR.B.in | | | MDR | | | MDR.A.out | |<-o--+-----+--o->| | MDR.B.out | | | ^ | | | | v | | | memory functions | | R->(memory)<-W | | ------------------- | | ^ | | R = read, W = write, | | | | | WFMC = wait for memory MAR.A.in | |--o->+-----+<-o--| | MAR.B.in complete | | | MAR | | | MAR.A.out | |<-o--+-----+--o->| | MAR.B.out | | | | ACC.A.in | |--o->+-----+<-o--| | ACC.B.in | | | ACC | | | ACC.A.out | |<-o--+-----+--o->| | ACC.B.out | | | | X.A.in | |--o->+-----+<-o--| | X.B.in | | | X | | | X.A.out | |<-o--+-----+--o->| | X.B.out | | | | Y.A.in | |--o->+-----+<-o--| | Y.B.in | | | Y | | | Y.A.out | |<-o--+-----+--o->| | Y.B.out | | | | | | | | .---|_| | | | | | | Y v B v ALU functions (three-bit F field) | | +---+ +---+ --------------------------------- | | \ V / 000 = B+Y 100 = B-Y | | F->\ / 001 = B 101 = not B | | +---+ 010 = B+1 110 = B-1 | | | 011 = B<<1 111 = B>>1 ALU.A.out |_|<-o-------+ --- 1) 7. 4 +----------+ +---------------+ +-------------+ | source |--|>-------bus------| combinational |--------| destination | | register | | | logic | .--| register | +----------+ | +---------------+ | +-------------+ R_out R_in |<---propagation---->|<----logic---->|<--setup-->|<--hold-->| | delay for bus | delay | time | time | 0.3ns 2ns 0.2ns 0ns Minimum clock cycle is 2.5ns 2) 7. 5 (following presentation in chapter 2, with one-word instruction) a) ADD #NUM,R1 1. PCout, MARin, Read, Select4, Add, Zin 2. Zout, PCin, Yin, WMFC 3. MDRout, IRin 4. Offset-field-of-IRout, Yin 5. R1out, SelectY, Add, Zin 6. Zout, R1in, End b) ADD NUM,R1 1. PCout, MARin, Read, Select4, Add, Zin 2. Zout, PCin, Yin, WMFC 3. MDRout, IRin 4. Offset-field-of-IRout, MARin, Read 5. R1out, Yin, WMFC 6. MDRout, SelectY, Add, Zin 7. Zout, R1in, End (question says to assume a two-word instruction) a) ADD #NUM,R1 1. PCout, MARin, Read, Select4, Add, Zin 2. Zout, PCin, Yin, WMFC 3. MDRout, IRin 4. PCout, MARin, Read, Select4, Add, Zin 5. Zout, PCin, Yin, WMFC 6. MDRout, Yin 7. R1out, SelectY, Add, Zin 8. Zout, R1in, End b) ADD NUM,R1 1. PCout, MARin, Read, Select4, Add, Zin 2. Zout, PCin, Yin, WMFC 3. MDRout, IRin 4. PCout, MARin, Read, Select4, Add, Zin 5. Zout, PCin, Yin, WMFC 6. MDRout, MARin, Read 7. R1out, Yin, WMFC 8. MDRout, SelectY, Add, Zin 9. Zout, R1in, End 3) LOAD M(X)+ // ACC <- memory[M+X]; X++; RTL --- // route PC across bus b into MAR and ALU, and then route // the incremented PC value across bus a back into PC step 1: MAR <- PC, PC <- PC + 1; // fetch instruction from memory and place in IR step 2: read, wfmc; step 3: IR <- MDR; // route X across bus b into Y and ALU, and then route // the incremented X value across bus a back into X step 4: Y <- X, X <- X + 1; // route address field across bus b into ALU, and route // the effective address across bus a into MAR step 5: MAR <- Y + address_part_of_IR; // route ACC into Y and read data from memory step 6: Y <- ACC, read, wfmc; // route memory value into ACC step 7: ACC < - MDR; control signals --------------- step 1: pc.b.out, mar.b.in, alu=b+1, alu.a.out, pc.a.in; step 2: read, wfmc idle step 3: mdr.b.out, ir.b.in; step 4: x.b.out, y.b.in, alu=b+1, alu.a.out, x.a.in; step 5: ir_addr. b.out, alu=b+y, alu.a.out, mar.a.in; step 6: acc.b.out, y.b.in, read, wfmc idle step 7: mdr.b.out, acc.b.in;