330 Spring 2011 -- Exam 1 Name: __________________ No calculators or other aids. 1. Give the power of 10 associated with these prefixes. (1 pt. each) kilo ________ giga ________ milli ________ nano ________ mega ________ tera ________ micro ________ pico ________ 2. Matching -- technology/performance terms. Write the correct term from the list into each blank. (2 pts. each) embedded computer chip clock cycle arithmetic mean Linpack desktop computer die CPU time harmonic mean Whetstone server wafer speedup geometric mean Dhrystone supercomputer CPI workload response time SPEC transistor Hertz memory throughput TPC-C a. _________________ a computer that provides computation, file storage, and/or printing to multiple users across a network b. _________________ a computer used inside another device running one or more predetermined applications c. _________________ a round slice of silicon upon which integrated circuits are built during the manufacturing process d. _________________ the program(s) being executed and their inputs e. _________________ used to summarize a set of rates f. _________________ measure of work done per unit time g. _________________ a synthetic integer benchmark, which was the basis of calculating relative MIPS values 3. Give typical values for current desktop / laptop computers. (6 pts.) a. clock frequency ___________ b. main memory size ___________ c. hard disk size ___________ 4. Find the execution time for a program that executes 8 billion instructions on a processor with an avg. CPI of 2.0 and a clock frequency of 4 GHz. (Show your work, including the CPU time equation you use.) (8 pts.) 5. For the following instruction set workload and cycle values, find the average CPI. (3 pts.) type | freq cycles -------+-------------- alu | 0.5 1 branch | 0.2 2 ld/st | 0.3 3 6. A redesign of the computer in question 5 is proposed that can achieve twice the clock frequency but requires that the load/store CPI value double. Would the redesign be faster, and if som what would be the speedup? (8 pts.) 7. Consider a computer that has an enhanced mode of execution that can speedup up execution by a factor of eight. For what fraction of the normal execution time must the 8x enhancement be used to achieve an overall speedup of 4? Show the result as a fraction. (8 pts.) 8. Matching -- logic terms. Write the correct term from the list into each blank. (2 pts. each) minterm don't care gate half adder flip-flop sum of products glitch PLA full adder register race condition fan-in ALU decoder shift register circuit depth fan-out latch multiplexer ring counter a. _________________ an input combination that is the and-product of each input variable in true or complemented form and represents one row in a truth table b. _________________ where the output of a circuit depends on small differences in signal timing c. _________________ unused value that can be arbitrarily assigned 0 or 1 d. _________________ undesired signal lasting only a short time e. _________________ a circuit in which n select values produce an exclusive output on one of 2**n output lines f. _________________ a circuit in which n select values route one of 2**n input values to the single output g. _________________ a circuit that arranges several flip-flops into a common read/write structure with a single clocking signal 9. Give a truth table to prove DeMorgan's Law A+B = A*B [that is, not(A or B) is equal to not(A) and not(B)]. (6 pts.) 10. Give (a) the truth table for a (one-bit-wide) full adder and (b) the circuit. For the circuit, you may use any of: a collection of gates, a PLA-based implementation, or a decoder-based implementation. (10 pts.) For the following questions, consider flip-flop types D and JK. characteristic excitation characteristic excitation D | Q(t+1) Q(t) Q(t+1) | D J K | Q(t+1) Q(t) Q(t+1) | J K ---+------- ------------+--- ------+------- ------------+----- 0 | 0 0 0 | 0 0 0 | Q(t) 0 0 | 0 x 1 | 1 0 1 | 1 0 1 | 0 0 1 | 1 x 1 0 | 0 1 0 | 1 1 0 | x 1 1 1 | 1 1 1 | ~Q(t) 1 1 | x 0 11. Show the design of a one-bit counter (modulo 2), progressing through these steps: (a) state diagram, (b) truth table, (c) logic expressions, (d) circuit implementation using a D flip-flop. There is no input, so the counter advances on each clock. No reset is required. Output is merely the state of the flip-flop. (5 pts.) 12. Show the design of a two-bit counter (modulo 4), progressing through these steps: (a) state diagram, (b) truth table, (c) logic expressions, (d) circuit implementation using D flip-flops. There is one input I, which has to be one for the counter to advance; when I=0, the counter remains in its current state. No reset is required. Output is merely the state of the flip-flops. (10 pts.) XC. Repeat question 12 using JK flip-flops. (up to 10 pts.)