CPSC 3300 - Spring 2017 Homework 8 Due at start of class on Tuesday, April 25 1. Consider a 4 GB byte-addressable main memory with a level-1 data cache that is eight-way set-associative, 32 KB in size, with 64 B lines. (a) How many total lines are there in cache? (not just per bank) (b) How many lines are there in a bank? (c) Show how the main memory address is partitioned into fields for the cache access and give the bit lengths of these fields. 2. Consider "streaming" applications that bring in large amounts of data but do not not reuse much of it. E.g., a video streaming application that accesses a 512 KB working set sequentially with the following (byte address) reference stream: 0, 2, 4, 6, 8, 10, 12, 14, 16, ... Assume a byte-addressed 64 KB direct-mapped cache with a 32-byte line size. (a) What is the miss rate of the address stream above? (b) How is the miss rate sensitive to the size of the cache or the working set? (c) How would you categorize the misses this workload is experiencing, based on the 3C model? 3. Assume a 256-byte main memory and a four-line cache with four bytes per line. The cache is initially empty. For the byte address reference stream (reads) given below circle which of the references are hits for the different cache placement schemes. Also, show the final contents of the cache. (The byte addresses are in decimal.) (a) direct-mapped 0, 16, 1, 31, 2, 32, 3, 17, 4, 18 (b) fully-associative with FIFO replacement 0, 16, 1, 31, 2, 32, 3, 17, 4, 18