CPSC 3300 - Spring 2017
Homework 4
Due at class time on Tuesday, Feb. 21
1. Consider a function F to compare two two-bit fields, x1 x0 and y1 y0,
and produce a one on output only if the two fields are the same.
(a) Consider using 2-input, 1-output PALs as shown in
http://en.wikipedia.org/wiki/File:Programmable_Logic_Device.svg.
(Actual PALs have many more inputs and outputs, but assume you
can get a chip like the one in the diagram.) Show a circuit
diagram for the two-bit comparator using these 2-input, 1-output
PALs. For each PAL give an 8-bit fuse list with 0 for blown fuse
(i.e., disconnect) and 1 for remaining fuse. Try to optimize the
circuit to require the fewest PALs possible. (Hint: A*B =
8'b10100000 = 0xa0 and A+B = 8'b10000010 = 0x82 -- note that a
single-variable AND term is allowed.)
(b) Consider using FPGA CLBs as shown in the lower half of
http://inst.eecs.berkeley.edu/~cs150/sp00/classnotes/u6.1/6_1_3.html.
(Assume that we will be using the unregistered output of theLUT,
that is, the 17th bit is 1.) Show a circuit diagram for the two-
bit comparator using one 4-input CLBs. Give the 16-bit LUT
configuration. (Hint: A*B + C*D = 16'b0001000100011111 = 0x111f.)
2. Consider a state machine that acts as a signal edge detector. There
is one input (I) and two outputs, positive (P) and negative (N). P=1
whenever I transitions from 0 to 1, and N=1 whenever I transitions
from 1 to 0. Assume the state machine starts in a state which records
a prior input of 0. The state machine behaves like this:
input I: 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 0
output P: 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0
output N: 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0
(a) Give the state diagram with the transitions annotated with
input/outputs - that is, the appropriate I/PN values.
(b) Give the state transition table with current state Q(t), input
I, next state Q(t+1), and outputs P and N.
Q(t) I | Q(t+1) P N
-------+-----------
(c) Give the simplified logic expressions for Q(t+1), P, and N.
3. Design a modulo-3 counter using two D flip-flops with the states
cycling as 00,01,10,00,01,.... (There is no input.)
(a) Give the state transition table with current state QA(t) and
QB(t) and next state QA(t+1) and QB(t+1). Use "don't care"
values where appropriate.
QA(t) QB(t) | QA(t+1) QB(t+1)
------------+----------------
(b) Simplify the logic expressions for the next state values.
(c) Draw the circuit.