CPSC 3300 - Spring 2018 Homework 2 Due at class time on Tuesday, Feb. 20 1. Consider A*( (~A) + B ) = A*B. Show by truth table that this is true. (10 pts.) A B | ~A | ~A + B | A*(~A+B) | A*B -----------+--------+------------+--------------+--------- 2. Given a 4-to-1 mux, input lines A and B, a true line (i.e., Vcc, which is logic 1), and a false line (i.e., Gnd, which is logic 0), show how you can construct the equivalent of an OR gate to produce A+B. (10 pts.) 3. Simplify the following Karnaugh maps for functions D, E, and F. (x is don't care) (10 pts. each) D \ BC A \ 00 01 11 10 +----+----+----+----+ 0 | 1 | 0 | 0 | 1 | D = fn(A,B,C) = ____________________ +----+----+----+----+ 1 | 0 | 0 | 1 | 1 | +----+----+----+----+ E \ BC A \ 00 01 11 10 +----+----+----+----+ 0 | 1 | x | 0 | x | E = fn(A,B,C) = ____________________ +----+----+----+----+ 1 | 1 | 0 | 0 | 1 | +----+----+----+----+ F \ CD AB \ 00 01 11 10 +----+----+----+----+ 00 | 0 | 1 | 1 | 0 | F = fn(A,B,C,D) = ____________________ +----+----+----+----+ 01 | 0 | 1 | 0 | 0 | +----+----+----+----+ 11 | 1 | 1 | 0 | 0 | +----+----+----+----+ 10 | 1 | 1 | 1 | 0 | +----+----+----+----+ 4. Consider a function F to compare two two-bit fields, x1 x0 and y1 y0, and produce a one on output only if the two fields are the same, that is, only if x1==y1 and x0==y0. (10 pts. each) (a) Show the truth table. (b) Write a simplified SOP logic function using only AND, OR, NOT operators to implement the two-bit comparison. 5. Consider a state machine that acts as a signal edge detector. There is one input (I) and two outputs, positive (P) and negative (N). P=1 whenever I transitions from 0 to 1, and N=1 whenever I transitions from 1 to 0. Assume the state machine starts in a state which records a prior input of 0. The state machine behaves like this: input I: 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 0 output P: 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 output N: 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 (10 pts. each) (a) Give the state diagram with the transitions annotated with input/outputs - that is, the appropriate I/PN values. (b) Give the state transition table with current state Q(t), input I, next state Q(t+1), and outputs P and N. Q(t) I | Q(t+1) P N -------+----------- (c) Give the simplified logic expressions for Q(t+1), P, and N.