CPSC 3300 - Spring 2018 Homework 4 Due at start of class on Thursday, April 26 1. Consider an array declared in C as "double a[400];". How many 64-byte cache lines are required to hold the complete array? 2. Consider a byte-addressed direct-mapped data cache design in which a 32-bit address is divided into these three fields: 20-bit tag, 9-bit index, and 3-bit offset. (a) How large is a line in number of bytes? (b) How many lines are in the cache? (c) How large is the cache in number of bytes? 3. Consider a 4 GiB byte-addressable main memory with a level-1 data cache that is direct-mapped with 1024 lines of 64 bytes each. For the byte address 0x00147ad0: (a) what is the offset value in hex? (b) what is the index value in hex? (c) what is the tag value in hex? 4. Consider a 4 GiB byte-addressable main memory with a level-1 data cache that is eight-way set-associative, 32 KiB in size, with 64-byte lines. (a) How many total lines are there in cache? (not just per bank) (b) How many lines are there in a bank? (c) Show how the main memory address is partitioned into fields for the cache access and give the bit lengths of these fields. 5. "Streaming" applications bring in large amounts of data but typically have little to no reuse of the data. Consider a streaming application that sequentially accesses the halfwords (i.e., 16-bit values) in a 512 KiB block in main mememory with the following reference stream (given in decimal): 0, 2, 4, 6, 8, 10, 12, 14, 16, ... Assume a byte-addressed 64 KiB direct-mapped cache with a 32-byte line size. (a) What is the miss rate of the address stream above? (b) If there is no reuse, is the miss rate sensitive to the size of the cache or to the size of the block in main memory? (c) How would you categorize the misses this workload is experiencing, based on the 3C model? 6. Assume a 256-byte main memory and a four-line cache with four bytes per line. The cache is initially empty. For the byte address reference stream (reads) given below circle which of the references are hits for the different cache placement schemes. Also, show the final contents of the cache. (The byte addresses are in decimal.) (a) direct-mapped 0, 16, 1, 31, 2, 32, 3, 17, 4, 18 (b) fully-associative with FIFO replacement 0, 16, 1, 31, 2, 32, 3, 17, 4, 18