CPSC 3300 - Spring 2018 Study Guide for Final Exam Coverage: question from Project 2 semiconductor memory (Appendix B) memory hierarchies and caches (chapter 5) 1. Be able to define or match these terms random access memory (RAM) static RAM (SRAM) dynamic RAM (DRAM) refresh memory cell array row decoder row address strobe (RAS) row buffer column decoder column address strobe (CAS) page-mode DRAM read-only memory (ROM) programmable ROM (PROM) erasable PROM (EPROM) memory hierarchy locality spatial locality temporal locality working set instruction cache data cache multilevel cache primary cache (level one, L1) secondary cache (level two, L2) cache hit hit rate (or hit ratio) hit time cache miss miss rate (or miss ratio) miss penalty refill burst transfer over memory bus for refill fetch policy (demand fetch or prefetch) placement policy (fully associative, set-associative, direct-mapped) replacement policy (LRU, pseudo-LRU, random, etc.) write-hit policy (write-through or write-back) write-miss policy (write-allocate or write-no-allocate) cache lines (often called cache blocks) valid bit dirty bit (also known as modified bit and changed bit) tag contents direct-mapped cache set-associative cache fully associative cache compulsory miss capacity miss conflict miss --------- did not cover and will not be on final exam --------- multiprocessor topics in chapter 6 cache coherency coherency miss (fourth C added to the three Cs cache miss model) snoopy protocol for shared bus, e.g., MESI write invalidate write update false sharing memory consistency --------------------------------------------------------------- 2. Be able to: A. Draw a block diagram (high-level circuit) showing the two-dimensional organization of a RAM and/or identify the components and signals required to access RAM. B. Draw a timing diagram of bus and RAM chip activity for a memory read. Be able to identify differences for burst transfer mode. C. Give typical capacity, latency, and block size values for the memory hierarchy components. D. Identify at least one example each of temporal and spatial locality of memory references. E. Given memory and cache parameters, give the tag, index, and offset field sizes within the main memory address. F. Given an address stream and cache parameters, determine the number of misses. G. Explain how row versus column access to a matrix affects cache misses. (E.g., discuss how misses were reduced in the matrix multiply example.) Be prepared to answer questions similar to the ones given in homeworks 4 and 5.