sequential circuits model of sequential logic (see figures B.10.1 and B.10.3) .---------------. | | input --->| |-------------------------------> output | combinational | | logic | .---------. .-->| |-> next state ->| memory |--. | | | | element | | | `---------------' `---------' | | | `-- current state <-------------------------------' when state changes occur based on clocking, the system is said to be synchronous synchronous systems are usally easier to design than asynchronous clocking (section B.7) repeated 1/0 signal with fixed cycle time high - phase 1 (phi 1) |<-cycle->| low - phase 2 (phi 2) ||| ____ ____ ____ 1 rising edge (a.k.a leading, positive)------>| | | | | | falling edge (a.k.a. trailing, negative)-------->| | | | | | |____| |____| |___0 phase lengths do not have to be equal (e.g., phase 1 can be a short pulse) memory elements (section B.8) latch - basic element of cross-coupled inverting gates (nands or nors) flip-flop - memory element that prevents a race condition - some authors state the difference is that flip-flops are clocked, but you will find "clocked latches" - other authors state the difference as a flip-flop is edge- sensitive (as opposed to "level-sensitive") - I'll use these distinctions: a latch is a simple storage device for which any changes in the input will immediately change the state of the output in a clocked latch, the above is true whenever the clock is high a flip-flop changes its state only once per clock cycle to deal with feedback in circuits, two types of flip-flops are used master-slave (but these are susceptible to "one's catching" - where a 0-1-0 glitch on an input line causes the same state change as for a normal input of 1 on that line) edge-triggered (positive/rising edge or negative/trailing edge) setup time - minimum time that input to an edge-triggered flip-flop must be valid prior to the edge hold time - minimum time that input to an edge-triggered flip-flop must be valid after the edge truth tables ("characteristic tables") Q(t) - current state Q(t+1) - next state set/reset FF JK FF data FF toggle FF (or delay FF) S R | Q(t+1) J K | Q(t+1) D | Q(t+1) T | Q(t+1) ------+------- ------+------- ----+------- ----+------- 0 0 | Q(t) 0 0 | Q(t) 0 | 0 0 | Q(t) 0 1 | 0 0 1 | 0 1 | 1 1 | ~Q(t) 1 0 | 1 1 0 | 1 1 1 | ? 1 1 | ~Q(t) JK avoids undefined state of SR using S=J*(~Q) and R=K*Q D avoids undefined state of SR using S=D and R=(~D) [note: in drawing cross-coupled nor circuits for flip-flops -- R, K, and Q are associated w/ same nor gate, even though block diagrams of flip-flops typically have S (or J) and Q at top; see Figure B.8.1] JK "excitation table" -- inverted table that shows the JK inputs required for a desired state change Q(t) Q(t+1) | J K -------------+----- (used for designing circuits based 0 0 | 0 d on state diagram and truth table) 0 1 | 1 d 1 0 | d 1 1 1 | d 0 equivalent representations state diagram (for a finite state machine) truth table current state input | next state output ----------------------+-------------------- Q(t) A | Q(t+1) W logic expressions circuit design sequence design with D flip-flops extra step for JK flip-flops ------------------------ ---------------------------- 1) word problem 2) state enumeration/assignment 3) state diagram 4) truth table 4A) expand truth table with columns for J,K signals using JK excitation table 5) K-maps for FF inputs and output 6) logic expressions from K-maps 7) circuit note: extra steps but will sometimes yield much simpler circuit further note: it's easy to add a Reset signal when the reset state is defined as all flip-flops are cleared to zero * some flip-flops directly provide clear (and preset) signals, * AND ~Reset with the normal inputs to the D flip-flops, or * AND ~Reset with normal J inputs and OR Reset with normal K inputs analysis sequence 1) circuit 2) logic expressions 3) truth table 4) state diagram analysis example 1 circuit +---. A ----->| . +-------+ |and |-->| D Q |------*--> W .-->| . | _ | | | +---' | Q |-> | | +-------+ | | | `---------------------------' logic expressions D-FF input [which is Q(t+1)] = A*Q(t) output W = Q(t) truth table Q(t) A | Q(t+1) W ---------+----------- 0 0 | 0 0 0 1 | 0 0 1 0 | 0 1 1 1 | 1 1 state diagram in Moore machine format (where output is a function of the current state) .---. .---. / v.===. .===./ \ 0,1 | |0/0| |1/1| | 1 \ /`==='^ /`==='^ / `---' `-----' `---' 0 states labeled with Q(t)/W and transitions labeled with A note: self-transition from 0 to 0 labeled with both inputs using a comma to separate note: state 0 is a trapping state (can never leave once there) analysis example 2 (note orientation of D-FF, with input on right hand side) \ +---. D-FF input and W output = A xor Q(t) A ---->\ \ `. | | xor .-*-->W Q(t) A | Q(t+1) W .->/ / ' | ---------+----------- | / +---' | 0 0 | 0 0 | | 0 1 | 1 1 | +------+ | 1 0 | 1 1 `-| D-FF |<--' 1 1 | 0 0 +------+ (acts like a T flip-flop) state diagram in Mealy machine format (where output is a function of both the current state and the input) 1/1 .---. .-----. .---. / v.===./ v.===./ \ 0/0 | | 0 | | 1 | | 0/1 \ /`==='^ /`==='^ / `---' `-----' `---' 1/0 states labeled with Q(t) and transitions labeled with A/X registers and shift registers assemblies of multiple flip-flops with common clock i3 i2 i1 i0 (inputs) | | | | +---------------+ clock --|> |--/-- control +---------------+ | | | | o3 o2 o1 o0 (outputs) control signals select functions such as: clear preset hold (maintain current value) serial-in parallel-in serial-out parallel-out left shift right shift clear and preset are typically asynchronous inputs that work independent of the clock; other are typically synchronous each bit position might have a design like this external_in | rshift_in ---. | .----- lshift_in .---. | | | | +-------+ | |0 1 2 3| s_1 s_0 | function | | |--- s_1 --------+------------ | | 4-to-1|--- s_0 0 0 | hold value | | mux | 0 1 | right shift | +-------+ 1 0 | load | | 1 1 | left shift | +-------+ | | D | | | | alternatively, a 00 | | D-FF | control select input clock -|--|> | could disable the clock | | Q | and thus hold the FF | +-------+ value steady for that | | clock cycle `--------* | out counters up, down, or bidirectional synchronous counters - clock is distributed in the same manner to all flip-flops ripple counters - output of some flip-flops are used as clock inputs for other flip-flops registered outputs on programmable logic devices allow you to easily build a sequential circuit