Processor Verification

In teams of four, write an 8-10 page report on functional verification and testing of processors. Each team member should read the Kevin Safford presentation (see link below) and then choose two of the eight papers. Team members should meet the week of October 21 (e.g., during class times) so that each team member can present and explain his or her two papers to the rest of the team. The team will then cooperate to prepare a report. The report should be structured in a manner similar to this:

1. Introduction to functional verification
   1. goal of functional verification
   2. impact of bugs
   3. placement of verification in design sequence
   4. typical resources devoted to verification (manpower, tools, etc.)
2. Aspects of functional verification
   1. testing of RTL (simulator) vs. actual silicon
   2. test code generation
      1. automatically-generated (random) tests
      2. hand-generated focused tests
      3. coverage analysis and improvement
   3. types of checking
      1. test case self-checking
      2. assertion checking
      3. signature checking
      4. special testing, e.g., bus protocol checking
   4. dedicated debug hardware
   5. evaluation of effectiveness of techniques, i.e., how many bugs are found using the various techniques
   6. stopping criteria
3. Difficult cases
   1. complex hardware, e.g., dynamic scheduling
   2. faults/traps/exceptions
   3. multiprocessor effects, e.g., cache coherency
   4. combinations of events
   5. number of possible states
4. Conclusions
   1. restatement of goal
   2. summary of approaches and effectiveness
   3. trends in verification
5. Bibliography

The above outline is not a "set-in-stone" requirement, but merely a starting point for each team. You may want to revise the outline as you read and present the papers. However, in presenting papers to the rest of the team, it would be good for each team member to organize his or her presentation according to the above outline. Within the paper, you are required to use section and subsection headers, and you are required to have the introduction, conclusions, and bibliography sections.

Papers

1. B. Turumella, et al., Design Verification of a Super-Scalar RISC Processor," FTCS-25, 1995. [HaL SPARC64]

2. M. Kantrowitz and L. Noack, "I'm Done Simulating; Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor," Design Automation Conference, 1996.

3. J. Monaco, D. Holloway, and R. Raina, "Functional Verification Methodology for the PowerPC 604 Microprocessor," Design Automation Conference, 1996.

4. S. Mangelsdorf, et al., "Functional Verification of the HP PA 8000 Processor," HP Journal, 1997.

5. S. Taylor, et al., "Functional Verification of a Multiple-Issue, Out-of-Order, Superscalar Alpha Microprocessor - The DEC Alpha 21264 Microprocessor," Design Automation Conference, 1998.

6. S. Ur and Y. Yadin, "Micro Architecture Coverage Directed Generation of Test Programs," Design Automation Conference, 1999.

7. R. Lee and B. Tsien, "Pre-Silicon Verification of the Alpha 21364 Microprocessor Error Handling System," Design Automation Conference, 2001.

8. Bob Bentley and Rand Gray, "Validating the Intel Pentium 4 Processor," Intel Tech Journal, Q1 2001.

9. J.M. Ludden, et al., "Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems," IBM JRD, vol. 46, no. 1, 2002.

Other Links

• Keith Safford, "Microprocessor Verification"

• UIUC ECE 371EMR - Microprocessor Verification, Test, and Design

[Course home page] [Mark's homepage] [CPSC homepage] [Clemson Univ. homepage]

mark@cs.clemson.edu