IBM Advanced Computing Systems -- Section on Arden House Planning

Mark Smotherman
last updated December 30, 2016

Planning the ACS at Arden House, August 1965

On August 3-7, 1965, full-scale planning for the ACS project began. The meeting was held at Arden House in Harriman, New York.

The presenters included:

Max Paley - introduction ("There is an air of destiny.")
Jack Bertram - architecture and programming
Harwood Kolsky - competition
T.C. Chen - S/360 Models 92 and 95
Herb Schorr - Project Y
Jim Pomerene - parallel design
Joseph Logue - circuits and packaging
Lee Shevel - memory technology
G. Nielson - schedules
A. DiMarco - technology
Claude Davis - I/O controls
Dick Arnold - programming systems
Jack Schwartz - NYU multiple-instruction-counter design
Gene Amdahl - summary

Questions of S/360 compatibility, multiprocessing, and time-sharing were designated for "later study". Conclusions from the discussions were presented on Friday evening (August 7) to John Haanstra.

The Project Y presentation included these highlights:

a universal processor
- 10 nsec cycle time
- compilation, file system, system control
a floating point processor
- 10 nsec cycle time
- "multiple decoding"
- "should execute on the average, more than one instruction per machine cycle" (1.5)
- "should have a lean machine cycle - 6 or 7 circuit levels/machine cycle"
- "pipelined A.U.'s"
- "6-8 machine cycle/storage cycle"
- "1/4 to 1/2 data storage references per instruction executed"
- "2-6 data references per storage cycle"
- memory queueing scheme
- "highly compilable"
- "transfer anticipation" (branches separated from instruction stream and executed early)
- "concurrent execution of transfers, arithmetic or logical, indexing, and loads or stores"
- "program-controlled look-ahead"
- logical components [note similarity to Stretch]
  - I-box - executes index ops and initiates loads and stores
  - E-box - executes arithmetic and logic ops using pipelined adder (3 cycle latency) and multiplier (3 cycle latency)
  - T-box - executes transfers as soon as test results and branch address are known
  - Store-box - waits for results from E- and I-box and initiates storage when operands are available
  - Load-box - initiates loads and checks with Store-box to see that up-to-date data values are obtained
  - Data memory control - generates storage requests on a FIFO for each box
  - Queue - holds storage requests that cannot be serviced immediately due to a storage conflict
- simulator results were given for unrolled matrix multiply for different instruction issue schemes
  - base design: "distribute each cycle ... up to 1 transfer; 2 arithmetic and logical; 2 index or 2 load/store"
  - increased burst rate design: "distribute each cycle ... up to 1 transfer; 2 arithmetic and logical; 2 load, store, index"
- basic short instruction format was 9-bit opcode and three 5-bit register specifiers
an I/O processor
- interface to head-per-track disks and tapes
- interface to low-speed devices
data memory
- 250,000 words
- 96-bit data memory word
- 16-way interleave
- 60-80 nsec cycle time
instruction memory
- 64,000 words
- 192-bit instruction memory word
- 4-way interleave
bulk storage
- 2,000,000 words
- 64-way interleave
- 250 nsec cycle time
- 2 msec to swap a program into the instruction memory

A letter from Bengt Carlson (of Los Alamos) was discussed as part a review of the marketplace. The suggestions in the letter included:

48-bit word size¹
one-word instruction length only
one set of registers, with 64 being the desirable size and one true/false bit per register
scaled indexing as an addressing mode ("true" indexing)
only loads, stores, and branches address memory

The letter gave several criticisms of the S/360 architecture and stated that he wanted a system that was "an order of magnitude easier to use" as well as as "an order of magnitude faster". He also stated that the system must include timesharing.

In his presentation, Gene Amdahl stated that customers take short cuts in measuring systems and that the speed of the CPU, especially floating-point, is the most important aspect. With regard to parallel systems, he gave an analogy of two mountains: the system support problem and the user's computational problem. He felt both were about the same size and argued for a single processor rather than two or four smaller processors. (This material appears to be a preview of the argument in his famous 1967 conference paper.)

Amdahl went on to argue for a S/360-compatible design, which he felt would provide 90-95% of the Project Y machine performance for at most 5-10% more hardware. He asserted that the system support mountain would be easier to scale by leveraging S/360 compatibility. He also felt that an incompatible system would frighten the Model 92 customers, since there would be no growth path.

A. DiMarko discussed two phases of circuit development. A first phase would use an improved ACPX technology, and a second phase would use 1 nsec circuits with 30-50 circuits per chip. Phase 2 chips would be mounted on 5" x 5" cards and 16" x 16" boards, and the chips would need to be liquid cooled.

Harwood Kolsky recorded that during the summary presentation on Friday evening Haanstra was critical of most of the proposals. He felt that there was too much generalizing and too few specific programs, with the result being "not a good start" and "not hitting [the] nail yet". With regard to some of the points described above, Haanstra questioned the single processor approach and was not in favor of S/360 compatibility. He also told the group to not worry about prices and that the project should "get the best circuits all things considered".

See Harwood Kolsky, Notes from Arden House planning sessions, August 1965. (46pp, 3.8M pdf) Courtesy of the Computer History Museum.

¹ 48 bits was not an unusual word size for the time. For example, Los Alamos had designed the MANIAC II computer based on a 48-bit word and had been using it since 1957. By 1965 Livermore was using three CDC computers with 48-bit word size, a 1604 and two 3600s, as well as the 60-bit CDC 6600. Both labs also had experience with 36-bit words in the IBM 704/709 scientific computer line as well as the 64-bit word size in the IBM 7030 (Stretch). John Savard lists a number of other computers in the 1960s that had a 48-bit word size.

With regard to floating-point precision and accuracy, Robert Gregory in a 1966 article in IEEE Transactions on Electronic Computers wrote:

In April, 1961, a week-long international conference on matrix computations was held at Gatlinburg, Tenn., under the sponsorship of the Oak Ridge National Laboratory and the Society for Industrial and Applied Mathematics. There was unanimous agreement among the participants at that conference that computer manufacturers should be urged to increase the word length on all future scientific computers to at least 48 bits.

The use of a 32-bit format for single-precision floating point along with choosing a base of 16 in the S/360 was not well received. See, for example, "The influence of machine design on numerical algorithms," by W.J. Cody of Argonne National Lab in the 1967 SJCC in which he compares floating-point errors in the CDC 3600 and IBM S/360. Cody introduced his paper by writing:

A great deal has been said and written recently about the poor arithmetic characteristics of computer designs, [original cites omitted] largely because anomalies long present in the floating point arithmetic of binary computers have suddenly been magnified in importance by the appearance of base 16 arithmetic.

Andres Padegs in "System/360 and beyond," in the 25th Anniversary issue of IBM JRD states:

Both the 32-bit and 64-bit [floating-point] formats use the same exponent size, with a base of 16. This was a departure from base 2 and was introduced to permit simpler circuitry and to reduce the frequency of pre-shift, overflow, and precision-loss post-shift in addition and subtraction.... The original System/360 architecture did not anticipate the significance of compatibility in the handling of overflow and the need for indicating the true result value on both overflow and underflow. Furthermore, it had overlooked the need for a guard digit in post-normalization. Both of these functions were changed in 1968, with all installed machines retrofitted.

Navigation within IBM ACS pages:

Back to first ACS page

Next section: ACS Staff