IBM Advanced Computing Systems -- Design sections

Mark Smotherman
last updated January 29, 2016

Hardware Design Tools and Design Process

Everything was a daily tradeoff between the capabilities of the compiler (for which Fran Allen and John Cocke are almost solely responsible), the architecture, and the engineering capability. We did it every day ... most individuals were involved in most of the discussions ... it was very fluid ... and the fluidity is why the simulators were so important.
-- Ed Sussenguth, personal correspondence

System Architecture Tools

The system architecture tools included an instruction set functional simulator that Lynn Conway later developed into a timing simulator.

Robert Riekert worked with Don Rozenberg and Lynn Conway at Yorktown on determining what simulation method or system to use. Riekert came up with ideas about how to build basic routines that enabled use of Fortran, as opposed to a language like Simscript. Riekert's ideas were important in gaining the simulation efficiency of Fortran, without losing much in terms of "ease of modelability" and "model readability". However, Riekert decided to stay at Yorktown, instead of going to California in 1965 with the other project members.

The following two illustrations of the simulator are taken from the MPM Timing Simulation report of August 1967. The first image shows the MPM parameters used for the simulation run.

The second image (yellow highlights added) shows the X-unit dispatch register part of the simulator output for a Crout reduction program for matrix decomposition.

In the simulation output, different instructions are represented by letters of the alphabet, where an instruction is assigned a letter on the basis of the instruction's half-word address mod 26. For the test program being run, the highlighted "Y" instructions in the output represent instances of the EXIT instruction that terminates the test program loop. There are three loop interations in this simulation run and 11 instructions in the loop body. Since the EXIT instruction is repeatedly fetched into the X-unit dispatch registers every 8 cycles, this represents an IPC (instructions per cycle) value of 1.375 during execution of this loop.

Logic Design and Engineering (Computer-Aided Design) Tools

A logic simulator was proposed by Lynn Conway; see "A Proposed ACS Logic Simulation System," October 1967
IBM had developed design automation for earlier systems based on an Automated Logic Diagram (ALD)
- See enlargement of an example ALD for the IBM 1401 (the full printer page from which this example is taken is here)
- For a description of the design automation process used for the IBM 1401, see R. Grim, "Information processing - from engineering drawing to manufacture," IRE Transactions on Product Engineering and Production, vol. 6, no. 3, September 1962, pp. 9-17. Grim describes how a logic designer starts with a preprinted grid to mark in the initial circuit design, as well as the batch-oriented process for changes: (1) the designer marks a printed ALD in green ink for deletions and red ink for additions; (2) a transcriptionist encodes the changes, (3) batch runs are made at periodic intervals to update the master logic tape, and (4) updated ALDs are printed after each batch run.
- The ALDs allowed rule-checking programs to be run against the master logic tape and catch a number of design errors before manufacture as well as driving automated testing after manufacture. ALDs also automated the production of manufacturing specifications such as bills of materials, wiring lists, and rework instructions to implement engineering changes.
- For a description of S/360 design automation, see P.W. Case, et al., "Solid logic design automation," IBM Journal of Research and Development, vol. 8, no. 2, April 1964, pp. 127-140.
The ACS project contracted with Computer Usage Development Corporation (CUDC) for its own Design Record Keeping System (DRKS) with a special input language. See Lynn Conway, "ACS Logic Design Conventions: A Guide for the Novice," November 1967. The CUDC group was led by Sandy Wilson and included Jack Powers.
An alternative Logic Description Language (LDL) was proposed by John Cocke. See Lynn Conway, "The Computer Design Process: A Proposed Plan for ACS," August 1968.

Design and Process Automation (Computer-Aided Manufacturing) Tools

IBM also contracted with CUDC for Chip Layout System (CLS) which was to help automate chip placement and module wiring.
In 1967 Jim Frego led the team of programmers assigned to develop software for an IBM 1800 computer to control via drilling and open-circuit/short-circuit testing of the boards. Jim states, "We had the x-y tables under computer control by Aug. 1967 and running the Drilling and Open Short Testing of boards by Sep. 1967." Jim also recruited programmers for converting engineering data files to manufacturing data files, with the goal of manufacturing the production ACS machines in Poughkeepsie. In June 1968 he became the manager for both the Manufacturing Software effort and the Pilot Line. "The Pilot Line consisted of the 4 women that did the manual module/board assembly and operated the Pilot Line Equipment. The automated Chip Placement/Bonding project was dropped and the wiring remained manual due to problems automating the process. A second shift of assemblers was added in early 1968."
A program named ALMS from IBM Research was investigated. It would produce list of chips for each MCM of board.
Larry Williams worked on a program to place chips on an MCM.

Sidebar - chip layout for the Amdahl 470 as compared to ACS

"My plan to use a larger chip size [for the Amdahl 470] for easier interconnection was improved upon by Fred Buelow, who learned there was a discarded, easily routed approach called a gate-array, which wasn't economical enough for chip manufacturers, but we could get a 100 gate chip, Large-Scale-Integration (LSI). This was phenomenal, for the ACS technology only provided about 35 gates, Medium-Scale-Integration (MSI), and took three or four months for a gifted man to route!" [ Gene Amdahl interview, IEEE SSCS E-news, 2007]

"We laid out [the Amdahl 470] chips so they looked just like the same density and the same connectivity requirements as a printed circuit board. We used printed circuit board routing to lay out our chips. This allowed us to get 100 gates on a chip, which was the first time that had been done. In ECL, the largest number anyone had ever done before was something like 35 gates, and that took normally about six or seven months to lay out. If there was a mistake, it would take another three or four months to fix it. But we laid these out in a matter of days using high-performance IBM 1130s for routing chips." [Gene Amdahl interview, IEEE Design and Test of Computers, 1997]

Hardware Design Schedule as of mid-1967

Acknowledgements: Thanks to Bill Mooney for providing the design schedule, to Jim Frego for information about the wiring and testing of modules, and to Jack Powers for the information about CUDC.

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