IBM Advanced Computing Systems -- Design sections

Mark Smotherman
last updated January 29, 2016

Hardware Design Tools and Design Process

Everything was a daily tradeoff between the capabilities of the compiler (for which Fran Allen and John Cocke are almost solely responsible), the architecture, and the engineering capability. We did it every day ... most individuals were involved in most of the discussions ... it was very fluid ... and the fluidity is why the simulators were so important.

-- Ed Sussenguth, personal correspondence

System Architecture Tools

The system architecture tools included an instruction set functional simulator that Lynn Conway later developed into a timing simulator.

Robert Riekert worked with Don Rozenberg and Lynn Conway at Yorktown on determining what simulation method or system to use. Riekert came up with ideas about how to build basic routines that enabled use of Fortran, as opposed to a language like Simscript. Riekert's ideas were important in gaining the simulation efficiency of Fortran, without losing much in terms of "ease of modelability" and "model readability". However, Riekert decided to stay at Yorktown, instead of going to California in 1965 with the other project members.

The following two illustrations of the simulator are taken from the MPM Timing Simulation report of August 1967. The first image shows the MPM parameters used for the simulation run.

ACS simulator parms
The second image (yellow highlights added) shows the X-unit dispatch register part of the simulator output for a Crout reduction program for matrix decomposition.
exampls ACS simulator output
In the simulation output, different instructions are represented by letters of the alphabet, where an instruction is assigned a letter on the basis of the instruction's half-word address mod 26. For the test program being run, the highlighted "Y" instructions in the output represent instances of the EXIT instruction that terminates the test program loop. There are three loop interations in this simulation run and 11 instructions in the loop body. Since the EXIT instruction is repeatedly fetched into the X-unit dispatch registers every 8 cycles, this represents an IPC (instructions per cycle) value of 1.375 during execution of this loop.

Logic Design and Engineering (Computer-Aided Design) Tools

Design and Process Automation (Computer-Aided Manufacturing) Tools

Sidebar - chip layout for the Amdahl 470 as compared to ACS

"My plan to use a larger chip size [for the Amdahl 470] for easier interconnection was improved upon by Fred Buelow, who learned there was a discarded, easily routed approach called a gate-array, which wasn't economical enough for chip manufacturers, but we could get a 100 gate chip, Large-Scale-Integration (LSI). This was phenomenal, for the ACS technology only provided about 35 gates, Medium-Scale-Integration (MSI), and took three or four months for a gifted man to route!" [ Gene Amdahl interview, IEEE SSCS E-news, 2007]

"We laid out [the Amdahl 470] chips so they looked just like the same density and the same connectivity requirements as a printed circuit board. We used printed circuit board routing to lay out our chips. This allowed us to get 100 gates on a chip, which was the first time that had been done. In ECL, the largest number anyone had ever done before was something like 35 gates, and that took normally about six or seven months to lay out. If there was a mistake, it would take another three or four months to fix it. But we laid these out in a matter of days using high-performance IBM 1130s for routing chips." [Gene Amdahl interview, IEEE Design and Test of Computers, 1997]

Hardware Design Schedule as of mid-1967

design timeline

Acknowledgements: Thanks to Bill Mooney for providing the design schedule, to Jim Frego for information about the wiring and testing of modules, and to Jack Powers for the information about CUDC.

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