Who are the Computer Architects?
last updated:
June 2024
- Considerations about the list
- Supercomputer processors
- VLIW processors
- Independence architecture processors (Intel IA-64)
- Mainframe processors
- Minisupercomputer processors
- Minicomputer and Superminicomputer processors (16 and
32-bit)
- Microcomputer processors
- Workstation processors (32 and 64-bit)
- Selected early workstations
- Wintel processors (16 and 32-bit)
- Multimedia processors
- LISP processors
- Java processors
- Other language-directed processors
- Stack processors
- Embedded processors
- DSP processors
- Selected game processors
- Acknowledgements
-
Revision history
The success and failure of high risk computer developments can quite often
be traced to a single individual. It is not accidental that unique persons
such as Gene Amdahl, Seymour Cray, Fred Brooks, and Bob Barton have become
recognized leaders in the computer architecture and design field. Their
reputations did not arise from a happy coincidence of being associated with
a successful project; rather, they stand out because of their ability to
generate a system wide concept, determine a course of action to get it
implemented, make the necessary tradeoffs and finally drive through all
obstacles to ensure completion of their vision.
Neil Lincoln, CDC
(from "It's really not as much fun building a supercomputer as
it is simply inventing one,"
in Kuck, Lawrie, and Samek, eds., High Speed Computer and
Algorithm Organization, Academic Press, 1977)
There is no doubt that Lincoln named four of the most influential computer
architects of the 1950s and 1960s. However, as a more recent architect
told me, people outside the design circles (sometimes even
meaning company executives) have bought into a myth: "in the '60s,
Computer Architecture Giants Walked The Earth, and we pathetic lame-o
descendants aren't fit to carry their slide rules." I agree that it is a myth.
It shouldn't be the case that just Amdahl, Cray, Brooks, and Barton are
recognized as giants in computer architecture and everyone else today is a
midget. There are many tremendously gifted people at work in instruction
set design and especially microarchitecture; so, I am publishing this list
to identify them and recognize their work.
The current format is a listing of an instruction set architecture (ISA)
and its architect(s), followed by implementations of that ISA and the
associated microarchitect(s)/designer(s).
The processors I am listing have been available for sale commercially,
and in most instances, I have categorized the processors by company.
Although I may extend the list back into and before the 1970s,
the current list mainly includes late 1980s and 1990s ISAs and
microprocessor implementations. I especially want to highlight
the high-performance (i.e., high-risk) implementations.
However, I approach this task recognizing several limitations of the list:
- The list may leave someone out and/or perhaps lead to disagreement over
the amount of someone's contribution.
I apologize in advance for mistakes and omissions.
- There are many excellent academic and industrial researchers in
computer architecture who have greatly influenced the design of current
processors but who have not served as the lead designer of a specific
ISA or chip. I leave their recognition to another list.
- I probably should do more to highlight a distinction made to me by
John Mashey. For some designs, there is a "clear architect who is THE
driving force" (perhaps even two people). In other designs, there might
be a team of people involved, and the architect has more of a
role of "collecting things together and being the editor of the
architecture document". In the later case, the success of an architecture
can really be credited to the wise assembly of different expertise.
I hope that listings of architecture teams will convey some of this distinction.
- I will leave many innovative processor designs that did not make it to
completion and market to footnotes or to another list (e.g., see the
Dead Supercomputer Society).
- There are many interesting computer systems that are based on existing
processors (e.g., Cray T3E using Alpha processors, SGI Origin using MIPS R10000
processors). I am not listing the system designers, but they are truly
computer architects, too.
- Finally, Tim Leonard pointed out that architecture management in a new
implementation of an existing instruction set architecture is a non-trivial
task. Maintaining compatibility and ensuring that an implementation meets a
spec requires new methods and processes that are also significant
contributions to computer architecture. ("With the S/360, IBM defined
and distinguished between architecture, implementation, and realization.
Afterward, every architecture needed a spec, a process for interpreting
and revising the spec, and verification tools for testing compatibility.
The S/360 Principles of Operation set the standard for subsequent ISA
specs. Digital's VAX Architecture Exerciser (AXE) set a new high for
methods of verifying compatibility.")
I would appreciate help in the form of your corrections, additions, and
other suggestions. I am especially interested in published articles
of these kinds:
- The history of a design, especially as it names the design team
members and their roles. Articles that contain interviews with
the architects and that go beyond "marketing talk" would be excellent.
- What was learned from the successes and especially from the "mistakes"
in a given design. (Yale Patt attempted to gather this kind of material
in the January 1989 special issue of IEEE Computer:
"Real Machines: Design Choices/Engineering Tradeoffs".)
I am also interested in URLs of web-published information.
I know of three books that help describe the environment and decision-making
constraints (e.g., politics) facing an architect:
- Charles Bashe, Lyle Johnson, John Palmer, and Emerson Pugh.
IBM's Early Computers. Cambridge, MA: MIT Press, 1986.
- Emerson Pugh, Lyle Johnson, and John Palmer.
IBM's 360 and Early 370 Systems. Cambridge, MA: MIT Press, 1991.
- Tracy Kidder.
The Soul of a New Machine. Boston: Little,
Brown, & Co., 1981. [story of the Data General MV/8000]
Harwood Kolsky wrote an excellent
analysis of the problems in the IBM Stretch project. His observations,
written in 1961, about problems such as a committee compromising and
including competing proposals in a single design and such as making
design decisions without proper cost and performance evaluation,
remain relevant 50 years later!
Robert Yung's PhD dissertation,
"Evaluation of a Commercial Microprocessor,"
UC Berkeley, SMLI TR-98-65, June 1998,
describes the design decisions for the UltraSPARC microprocessor.
Chapter 3 of his dissertation discusses design principles and pitfalls,
and Chapter 6 discusses lessons learned with respect to design
methodologies, business decisions, and technology considerations.
More recently, Bob Colwell has discussed some of his experiences at Intel
in the 1990s while working on the Intel P6 and early phases of the Pentium 4
in
Things CPU Architects Need To Think About (abstract), Stanford University
Computer Systems Laboratory, EE380 Colloquium Series, Feb. 18, 2004.
[available on the web, Windows Media, 80+ mins.] Bob has also written
a book describing his experiences, mainly from a project manager perspective,
called
The Pentium Chronicles, IEEE-CS/Wiley-Interscience, 2006, and in
2009 was interviewed by Paul Edwards for an
oral history (164 pp pdf).
Also, some articles that describe the design and verification process
include:
- Matt Reilly,
"Designing an Alpha Processor," IEEE Computer, July 1999,
pp. 27-34.
- Chuck Moore,
"Getting It Right," IEEE Micro, March/April 2003.
- Chuck Moore,
"Managing the Transition from Complexity to Elegance:
Knowing When You Have a Problem," IEEE Micro, Sept./Oct. 2003.
- Chuck Moore,
"Managing the Transition from Complexity to Elegance:
Design Convergence," IEEE Micro, Jan./Feb. 2004.
Mark Smotherman
See also the list of
machine designs admired by computer architects.
... much more to do!
Astronautics
- Astronautics ZS-1 (Decoupled Architecture), 1987 - Jim Smith
Control Data Corporation (CDC)
- 6600, 1964 - Seymour Cray (project lead) and Jim Thornton (CPU)
- nucleus of early team consisted of Seymour Cray, Jim Thornton,
Les Davis, Dean Raush, Garner McCrossen, and Paul Kristensen
- Cray - led PPU and memory system designs
- Thornton and Davis - led CPU design
- Cray and McCrossen - led software design, including a FORTRAN
compiler and simple OS
- Jim Thornton,
"The CDC 6600 Project,"
IEEE Annals of the History of Computing, vol. 2, no. 4,
Oct.-Dec. 1980, pp. 338-348. (on-line abstract)
- Jim Thornton,
Design Of A Computer - The Control Data 6600,
Scott, Foresman and Co., 1970. (on-line copy of book, 18 MB pdf)
-
Gordon Bell's talk on Cray
-
"Reminiscences of computer architecture and computer design
at Control Data Corporation," oral history interview at CBI,
moderated by Neil R. Lincoln, 1975
- 7600, 1969 - Seymour Cray
- 8600 (cancelled)
- Cyber 70/170 (continuation of 6600/7600 line)
- Cyber 180/990 - Ron Hintz (chief architect)
- Tom Lane, Jim Smith, ...
- used branch prediction and "conditional issue" (i.e., speculative
execution) [first use of two-bit counter for branch history?]
- Star-100, 1974 - Jim Thornton, Neil Lincoln (became chief architect
and project manager in 1972)
- Cyber-205, 1980 (redesign of Star-100), Neil Lincoln (chief architect)
Cray Research (CRI)
- Cray-1, 1976 - Seymour Cray (architect), Lester Davis (chief engineer)
- X-MP, 1982 - Steve Chen
- M. August, G. Brost, C. Hsiung, and A. Schiffleger,
"Cray X-MP: The Birth of a Supercomputer,"
IEEE Computer, January 1989, pp. 45-54.
- Cray-2, 1985 - Seymour Cray
- Y-MP, 1988
- C90, 1990
- T3D, 1993 (MPP, using DEC Alpha processors)
- T3E, 1995
[Seymour Cray left CDC in 1972 to found CRI. He left CRI in 1989 to
found CCC. CRI merged with SGI in 1996. A separate Cray Research
business unit was later created by SGI in 1999 and sold to Tera in 2000.
Tera renamed itself as Cray, Inc.]
Cray Computer (CCC)
[CCC started in 1989 and closed in 1995. Seymour Cray founded SRC in 1996.]
ETA
- ETA-10, 1986, Neil Lincoln (chief architect)
- instruction-set compatible with the CDC Cyber 205
- high-end models were liquid nitrogen cooled and
had up to eight processors
- low-end models were air-cooled and had up to two processors
- Lloyd Thorndyke (president and CEO),
Tony Vacca (circuit, memory, packaging, and CAD leader),
Dale Handy (manufacturing manager), and Lee Kremer (operations)
- references
- Tony Vacca,
"First-Hand: The First CMOS and the Only Cryogenically
Cooled Supercomputer", 2017
-
"ETA Systems Hardware Technologies (1983-88)", 2017
- Lloyd Thorndyke,
"The Demise of ETA Systems", in K. Ames and A.
Brenner (eds.), Frontiers of Supercomputing II: A National Reassessment,
1994, pp. 489-496.
- Rob Peglar,
"The ETA Saga", 1990
Fuji Film
- FUJIC, 1956 - Okazaki Bunji
(first Japanese electronic computer)
Fujitsu
- FACOM 230-75 APU, 1977 - Osamu Miwa
- VP100 and VP200, 1983
- VP400, 1986 - Keiichiro Uchida
- VP2000, 1990 - Yuji Oinaga
- VPP500, 1993 - Moriyuki Takamura
- VPP5000, 1999 - Yuji Oinaga
Hitachi
- HITAC M-1801 AP, 1978
- HITAC S-810, 1983
- HITAC S-820, 1988
- HITAC S-3800, 1993
NEC
- SX-1 and SX-2, 1985
- SX-3, 1989
- SX-3R, 1992
Supercomputer Systems, Inc. (SSI)
- SS-1, 1988-1993 (cancelled) - Steve Chen (see US patent 5,197,130)
SiCortex
- ICE9, 2005 - Jud Leonard
- six-core SOC design with each core having in-order issue of up to
two MIPS-64 instructions
- the SOC also had a shared coherent L2 cache, DMA engine, two memory
controllers, network switch, and PCI Express interface
- SiCortex was founded by John Mucci, Matt Reilly, and Jud Leonard
- company built and sold more than 80 systems of up to 5,832 cores each
- compute nodes were interconnected by a network based on the Kautz graph
- Bob Supnik, then Kem Stewart, ran engineering
- operated from 2004-2009 in the old red brick mill complex
in Maynard, MA, that was DEC's headquarters
- several members of the SOC design team came from
DEC-Hudson's Alpha chip development group; the first generation
chip taped out 21 months after hiring the team
- acquired the PathScale compilers that were developed as the MIPSPro
compilers for the MIPS R10000 by Tom McWilliams, Jeff Rubin, Jeff
Broughton, and Fred Chow (all of whom had worked together on the
LLNL S1);
Cray bought the compiler suite when the SiCortex assets were sold
- see
2009 interview with Matt Reilly
Tera
- Tera
(multithreaded VLIW) - Burton Smith
- descended from Deneclor HEP and SRC Horizon
Texas Instruments
- TI-ASC, 1972 -
- H. Cragon and W.J. Watson, "The TI Advanced Scientific Computer,"
IEEE Computer, January 1989, pp. 55-64.
Thinking Machines, Inc. (TMI)
- Connection Machine, 1981 - Danny Hillis
- CM-1 (1985) - hypercube with single-bit processors
- CM-2 (1987), CM-2a, CM-200 - added FPUs
- CM-5 (1993), CM-5E - fat tree with SPARC processors
... more to do!
See multimedia processor section.
Analog Devices
- TigerSHARC, 1999 - Jose Fridman
Apollo (see Apollo entry in
workstation processor section)
Broadcom
- FirePath, 2000 - Sophie Wilson
- designed at startup Element 14, bought by Broadcom
- two-way LIW, with each instruction providing SIMD capabilities
Culler Scientific Systems
- Culler-7, 1986 - Glen Culler (lead), Bob Pearson,
John Richardson, Mike McCammon, and Dave Probert
(see
Culler-7 web page)
Cydrome
- Cydrome Cydra 5, 1988 - Bob Rau, Ross Towle, David Yen, and
Wei Yen
- Ross Towle - compiler
- worked for Gary Beck on the processor: Tom Anderson,
Joe Bratt, John Brennan, Ray Bulger, Gulbin Ezer,
Tim Fu, Craig Nelson, Frank Reid, Chris Rockwood,
and Steve Wilson. Don DeSota later joined and
managed part of the team.
- worked on the memory system - Ed Wolff and Norman Yeung
- worked for Jack Kister on the I/O system: Gil Lauer, Jack Mills,
David Roe, and Mohammed Seth
- others who contributed to hardware and software efforts:
Jim Dehnert, Stimson Ho, and Mike McNamara
- Peter Hsu and Mike Schlansker did the groundwork for the Cydra 10
(which did not get further than a paper design before the company folded)
- Peter Hsu went to MIPS and the MIPS R8000 was greatly influenced by the
Cydra designs
- Bob Rau, David Yen, Wei Yen, and Ross Towle,
"The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions,
and Trade-offs," IEEE Computer, January 1989, pp. 12-35.
- Gary R. Beck, David W. L. Yen, and Thomas L. Anderson,
"The Cydra 5 Minisupercomputer: Architecture and Implementation,"
The Journal of Supercomputing, 1993.
(also appears in B. R. Rau and J. A. Fisher (eds.),
Instruction-Level Parallelism, Kluwer Academic Publishers, 1993.)
FPS (Floating Point Systems)
- AP-120B, 1975 (array processor for signal processing)
- Alan Charlesworth and George O'Leary
- FPS-164, 1980 (array processor for scientific computing)
- FPS-264, 1985 (ECL version of FPS-164)
- non-VLIW products
- T-series Hypercube, 1986
- FPS-500, 1988 (revised version of Celerity 6000 minisupercomputer)
- Howard Thrailkill, "FPS Computing: A History of Firsts,"
in Frontiers of Supercomputing II: A National Reassessment,
1994, pp. 497-503.
Fujitsu
- Tacyon - Toshiaki Kitamura
Intel
- Intel i860 (N10), 1989 - Les Kohn
- RISC-like processor with dual instruction mode (LIW)
- See discussion of design team in Tekla Perry, "Intel's secret is out,"
IEEE Spectrum, April 1989, pp. 22-28. A picture of the design team
is on the cover of this issue.
- exposed pipelines were criticized for their effect on
context switch complexity and latency,
later the chip was used by many as a graphics accelerator
- i860XP (N11) - David Perlmutter (Chief), Michael Kagan (lead)
- an extension to N10, with MP support (enable physical snooping),
new process, and better performance.
Multiflow
- Multiflow TRACE, 1988 - Dave Papworth (co-chief),
Paul Rodman (co-chief), and John O'Donnell
- Based on ideas of Josh Fisher
- compiler folks: John Ruttenberg, Geoff Lowney, Tom Karzes,
Stefan Freudenberger, Cindy Collins, Woody Lichtenstein
(worked on the Culler-7)
- hardware team: Chandra Joshi (memory), Richard Lethin
(floating point), John Feehrer, Mauro Lupero (I/O), Bob Colwell
- operating systems team: Bob Nix, Doug Gilmore, Ben Cutler,
Chris Ryland
- for a description of Multiflow as a startup company,
see Elizabeth Fisher,
Multiflow Computer: A Start-up Odyssey,
CreateSpace Independent Publishing Platform, 2013
Tera (see supercomputer processor section)
Texas Instruments
Name due to Josh Fisher and Bob Rau.
Explicitly encoded information on instruction independence is
placed in the instruction format by the compiler.
Difference from VLIW is that hardware does the scheduling.
Example prototype is Burton Smith's Horizon processor.
... more to do!
Intel
- Intel IA-64, 1997 - John Crawford, chief architect
- first discussions about joint venture in December 1993
- cooperation announced in June 1994
- joint ACM committee (architecture, compilers, microarchitecture)
- five Intel members:
- John Crawford (chief architect for overall effort)
- Hans Mulder (architecture)
- Harsh Sharangpani (microarchitecture and x86 floating point
compatibility)
- Kent Fielden (compilers)
- Jack Mills (architecture and performance evaluation)
- five HP members:
- Jerry Huck (lead architect for HP)
- Rajiv Gupta (architecture, Wide-Word background)
- David Fotland (microarchitecture, PA-RISC background)
- Dale Morris (architecture, PA-RISC background)
- Carol Thompson (compilers)
- partially based on P7 effort at Intel guided by Don Alpert
- partially based on PA-Wide-Word effort at HP Labs guided
by Bill Worley, 1990-1993; also called SP-PA (Super-Parallel
Processor Architecture) [see
Joel Birnbaum's talk at Microprocessor Forum]
- Crawford and Huck introduced the EPIC philosophy at the
1997 Microprocessor Forum
-
IEEE Micro special issue on IA-64
-
IEEE Computer, February 2000, article by Schlansker and Rau on EPIC
- see also
Historical background for HP/Intel EPIC and IA-64
- Itanium implementations
- Merced, 2001 - first implementation, Intel team
- Don Alpert, engineering manager 1993-1998;
Avtar Saini and Gary Thomas were first two project managers;
project converged under final project manager Gadi Singer
- Harsh Sharangpani, lead microarchitect
- Ken Arora, lead designer for control logic
- Ken Shoemaker, lead designer for x86 compatibility
- Sharangpani introduced the
Itanium microarchitecture
at the 1999 Microprocessor Forum; see also
Linley Gwennap, "Merced shows innovative design,"
Microprocessor Report, October 6, 1999, pp. 1-6
- Harsh Sharangpani,
"Intel Itanium Processor Core" (pdf), Hot Chips 12 slides,
August 2000.
- Harsh Sharangpani and Ken Arora, "Itanium Processor
Microarchitecture," IEEE Micro, Sept./Oct. 2000, pp. 24-43
- McKinley, 2002 - second implementation, HP team
- Don Soltis (and others?)
- Madison was 2003 revision
- Montecito, 2006
- Cameron McNairy (and others?)
- dual core; 2-way multithreading per core
- Montvale was 2007 revision
- Tukwila, 2010
- Eric DeLano (chief architect)
- quad core; 2-way simultaneous multithreading per core;
Quick Path Interconnect
StarCore
- SC140, 1999 - Zvika Rozenshein
- up to six instructions in an execution set
- timing of an execution set is set to the maximum time of the
instructions within that set
- prefix words within an execution set can control an efficient
hardware looping facility and conditional execution
- SC110, 2001
- up to three instructions in an execution set
Texas Instruments
to be done
Burroughs
- B5000, 1963 - Bob Barton
- B5500, 1964 -
- B6500, 1969 - Jake Vigil (microarchitecture) and Ben Dent (software)
- B7500 -
- B5700, 1970 -
- B6700 -
- B7700 -
- A-series -
- B1700 - Bob Barton and W.T. Wilner
- B1712, B1726 - First generation hardware implementing a reloadable
microarchitecture. Interpreters were kept in main memory and were
swapped by the OS (MCP) as different language codes ran.
- B1835, B1855, B1865 - upgrades with a cache memory for the interpreter
- B1910, B1955, B1965 - TTL-based implementations of the architecture.
The B1900 was designed by a group led by Ed (Bud) Keeley. Bill Sprouse
and Frank Williams were the main hardware designers with Steven Tsai,
Steven Amic, and Steve Wilson also working on the CPU. The I/O
subsystem group was led by Jerry Wygant. Todd Barth did the disk
controller.
Control Data Corporation (CDC)
- 1604, 1960 - Seymour Cray
(see
Gordon Bell's talk on Cray)
- 3600, 1963 - Charles Cassel, Max Goldberg, Charles Hawley,
and Ken Thiede, architecture;
Don Pagelkopf, chief engineer;
Ron Hintz and Stan Aschenbrauner, CPU design;
Charles Hawley, memory and I/O channels;
Sam Slais, tape controller;
Sid Anderson, card reader/punch
Digital Equipment Corporation (DEC)
General Electric (GE) / Honeywell Information Systems (HIS)
-
Several GE papers in Winter 1995 IEEE Annals of the History of Computing
- Honeywell acquired GE computer business in 1970
- ERMA (check-processing system for Bank of America, based on MICR)
prototype at SRI, 1955 - Tom Morrin (SRI);
production model was GE-100, 1959 - Barney Oldfield;
later upgraded to GE-210
- GE-302/312 (industrial control), 1957 - Arnold Spielberg
- GE-225 (derived from 312), 1962 - Arnold Spielberg;
later 215 and 235 (DTSS, 1964) models added;
model 265 was a 235 with DATANET 30 terminal controller
- GE-635, 1963 - John Couleur
- genesis was in military work on MISTRAM computer, ca. 1959
- John Couleur, "The core of the Black Canyon Computer Corporation,"
IEEE Annals of the History of Computing, 17, 4, 1995, pp. 56-60.
- ran GECOS; other models included 615 and 625
- renamed Honeywell 6000 series (GECOS renamed GCOS); some models
extended with decimal/COBOL-oriented inst. set called EIS
- follow-ons were Series 60/Level 66, then DPS-66
- GE-645 (MULTICS - Multiplexed Information and Computing Service), 1965 -
John Couleur (GE) and Edward Glaser (MIT)
- Frank Fahrlander wrote a system simulation;
Jim Haynes headed up the 645 hardware prototype;
G.A. Oliver worked on the design of the segmentation scheme; and,
Ed Thelen helped design the GIOC
- John Couleur invented the TLB and indicates that this was an
important factor in MIT and Bell Labs choosing GE over IBM for
Project MAC
- added advanced segmented and paged memory system along with protection
rings to 635 processor; initial plans for 32 protection rings reduced
to 8 rings in final hardware; 645 ran fairly slow (wags said MULTICS =
"Multiple Useless Large Tables in Core Simultaneously"); users beyond
Project MAC allowed on single operational system at MIT in 1969
- follow-ons were Honeywell 6180 in 1972, then Series 60/Level 68,
then DPS-68, then DPS-8/M
-
Multics Repository at Stratus Computer
-
Tom Van Vleck's MULTICS pages
Fujitsu
- FACOM100, 1954 - Toshio Ikeda (relay computer)
- FACOM128A, 1956 - Toshio Ikeda (scientific relay computer)
- FACOM128B, 1958 - Toshio Ikeda
- FACOM138A, 1957 - Toshio Ikeda
- FACOM200, 1958 - Toshio Ikeda
- FACOM201, 1960 - Toshio Ikeda
- FACOM202, 1960 - Toshio Ikeda
- FACOM212, 1959 - Toshio Ikeda
- FACOM222P, 1961 - Toshio Ikeda (transistorized)
- FACOM230-50, 1964 - Toshio Ikeda
- FACOM230-60, 1968 - Toshio Ikeda
- FACOM230-75, 1973 - Toshio Ikeda
- M-190, 1975 - Toshio Ikeda
- M-200, 1978 - Yoshioka Yosiro
- M-380, 1982 - Takamitsu Tuchimoto
- M-780, 1986 - Kazuyuki Shimizu, Hirosada Tone
- M-1800, 1991 - Yuji Oinaga
- GS8600, 1996 - Hirosada Tone, Aiichiro Inoue
- GS8800, 1998 - Hirosada Tone, Aiichiro Inoue
- Chaos (the preliminary conceptual work for GS8800B) -
Robert Tomasulo, Bob Maier, Mark Nielson
- GS8800B, 1999 - Aiichiro Inoue, Takeo Asakawa,
Tsuyoshi Motokurumada, Kuniki Morita
- GS8900, 2000 - Aiichiro Inoue
- GS21-600 - Aiichiro Inoue
- GS21-900 - Aiichiro Inoue
International Business Machines (IBM)
- 650, 1953 - Ernest Hughes (chief architect) and Frank Hamilton (chief
designer)
- 701, 1953 - Nat Rochester (chief architect) and Jerrier Haddad
(engineering manager)
- 702/705, 1953/1954 - Werner Buchholz
- 704, 1954 - Gene Amdahl
- NORC, 1954 (Naval Ordnance Research Calculator) - Byron Havens
(chief engineer)
- 7030 (Stretch), 1955-1961 - Stephen Dunwell (project manager),
Eric Bloch (engineering manager);
Gerrit Blaauw, Fred Brooks, Werner Buchholz, John Cocke, and
Harwood Kolsky (others ...)
(Gene Amdahl contributed to the design before he resigned in 1955)
- 7070 was a transistorized descendent of the 650
- 7080 -
- 709/7090 -
(Gene Amdahl contributed to the 709 design before he resigned in 1955)
- 7040/7044 -
- 7094 -
- 7950 (Harvest), 1958-1962 - James Pomerene
- 1401, 1959 - many people involved with major contributions from
Francis Underwood
- 1620 -
- System/360, 1964 ("360 degrees of data processing") -
- lead architects were
Fred Brooks (project manager),
Gene Amdahl (architecture manager), and
Gerrit Blaauw (second architect and manual author);
also involved with the design were Richard Case, George Grover,
William Harms, Derek Henderson, Paul Herwitz, Graham Jones,
Andris Padegs, Anthony Peacock, David Reid, Willian Stevens,
and William Wright
- model 20, 1966 - G.F. Nielsen (engr. mgr.)
- model 30, 1965 - Jack Greene (engr. mgr.) [Endicott]
- model 40, 1965 - John Fairclough (engr. mgr.) [Hursley;
Grant Bush key liaison]
- model 50, 1965 - John Hipp (engr. mgr.), Gerry Paul (CPU mgr.)
[Poughkeepsie; Pete Fagg (systems mgr.)]
- model 65, 1965 - Joe Brown and Dick Case (engr. mgrs.),
Frank Wise (I/O channel mgr.)
[Poughkeepsie; Pete Fagg (systems mgr.)]
- model 75, 1966 - Carl Christiansen, then
Daniel Doody (engr. mgrs.), Richard Holleran (CPU mgr.),
Leo Hasbrouk (instruction processing unit),
Wes Stetler (arithmetic unit),
William Wissick (bus control unit),
Earl Miller (maintenance unit, power, and packaging),
Frank Wise (I/O channel mgr.),
Joe Tondreau (?) (program coordination and admin. mgr.)
[Poughkeepsie design / Kingston built; Phil Stoughton, then
Pete Fagg (systems mgr.)]
- model 67, 1966 - Joe Brown (engr. mgr.), Gene Amdahl (address relocation)
- model 91, 1967 - Mike Flynn, Robert Tomasulo (FP unit)
- highly parallel FP unit; first [?] use of fetching down taken and
untaken branch paths
- model 85, 1969 - W.R. Demmer (engr. mgr.),
Stan Pitkowsky (CPU mgr.); Don Gibson, Carl Conti,
and Jim Shelly worked on cache;
John Liptay designed the instruction unit;
(others from the model 65 engineering team)
- S/370 - Richard Case (systems architecture mrg.); Andres Padegs,
Ron Smith, many programmers and engineers
- model 135, 1972 - (developed from S/360 model 25?)
- model 145, 1971 -
- model 155, 1971 - M. Monachino (CPU mgr.)
- model 165, 1971 - (developed from S/360 model 85)
- 3031, 1978 - (developed from S/370 model 158)
- 3032/3033, 1978 - (developed from S/370 model 168)
- 3033 - John Liptay was the chief engineer and worked with
Jim Rymarczyk on the I-unit. Pat Gannon and Ken Sze worked
on the Storage Control Unit, Ken Parchinski worked on the
E-unit, Danny Casper and Bob Capowski worked on the I/O
channels, and Herb Driver did the microcode.
- 4300, 1979 - (developed from S/370 model 148)
- 3081, 1981 - Sam Levine, Joe Wetzel
- 370/XA architecture, 1983 - Andres Padegs, Ron Smith, Julian Thomas,
many programmers and engineers (programming mgt. included:
Mike Mall and Rick Baum)
- (available on 3081)
- 3090, 1985 - Julian Thomas, Werner Bucholz, and Ron Smith (architects),
Les Garcia (engineering), Stuart Tucker (I-element and vector unit),
Ron Linton (microprogramming), Henry Brandt (BCU), Joe Datres (memory)
- ESA/390 architecture, 1990
- ES/9000
- high-end models (9022 CPU) - John Liptay
- CMOS generations
- G1, 1994 -
- G2, 1995 -
- G3, 1996 -
-
G4, 1997 - Webb and Liptay
- G5, 1998 - (added BTB)
- G6, 1999 -
- z/Architecture, 64 bit extensions, 2000
- z900, 2000 -
- z990, 2003 -
- z9, 2005 -
- z10, 2008 -
Univac
... more to do!
Alliant
- FX/8, 1985
- The ISA was basically an emulated Motorola 68012, augmented with
vector instructions and parallel processing constructs. The
special parallel processing features (hardware, self-scheduled,
DO ALL and DO ACROSS functions) were inspired by work done at
University of Illinois and further developed by Alliant's founders,
especially Ron Gruner and Craig Mundie.
- The primary architect for the vector ISA augmentations was
Mat Myszewski, with contributions from Josh Rosen and Stan Lackey,
who were the chief hardware implementers for the CPUs (CEs in
Alliant-speak).
- Mike Ziegler was the primary architect for the overall system
configuration and the cache and memory system in particular.
- The parallel processing hardware (Concurrency Control Unit) and
the instruction set extensions that made use of it were architected
by Mat Myszewski and Mike Ziegler. Jim Veres was the primary
implementer of this hardware and also contributed to the design.
- Jim Veres was also responsible for the overall IO system architecture.
- Stan Lackey, Jim Veres, and Mike Ziegler, "Supercomputer Expands
Parallel Processing Options," Computer Design, August 15, 1985, p. 76.
- For a description of the startup environment of Alliant, see the
interview of Ron Gruner in Chater 32 of Jessica Livingston, Founders
at Work: Stories of Startups' Early Days, Apress, 2007.
Ardent
- Titan, 1988 - Bell, Miranker, Rubinstein, and Sanguinetti?
- G. Miranker, J. Rubinstein, and J. Sanguinetti, "Squeezing a Cray-class
supercomputer into a single-user package," COMPCON, San Francisco,
Feb. 1988, pp. 452-456.
- G. Bell, G. Miranker, and J. Rubinstein, "Supercomputing for one,"
IEEE Spectrum, 25, 4, April 1988, pp. 46-50.
- R. Allen, "Unifying vectorization, parallelization, and optimization:
The Ardent compiler," Proc. 3rd ICS, Boston, May 1988, pp. 176-184.
- J. Sanguinetti, "Micro-analysis of the Titan's operation pipe," Proc.
ICS, St. Malo, July 1988, pp. 190-196.
- T. Diede, C. Hagenmaier, G. Miranker, and J. Rubinstein,
"The Titan graphics supercomputer architecture," IEEE Computer,
21, 9, Sept. 1988, pp. 13-31.
- G. Miranker, J. Rubinstein, and J. Sanguinetti, "Getting it right
the first time: The Ardent design methodology," COMPCON, San Francisco,
Feb. 1989, pp. 529-533.
- B. Borden, "Graphics processing on a graphics supercomputer,"
IEEE Computer Graphics and Applications, July 1989, pp. 56-62.
- R. Allen, "Exploiting multiple granularities of parallelism in a
computer," COMPCON, San Francisco, Feb. 1990, pp. 634-640.
-
Dan Siewiorek and Phil Koopman, The Architecture of Supercomputers:
Titan, a case study, Academic Press, 1991.
- Tom Anderson, Gary Beck, Joe Bratt, and Chris Rockwood came to
Ardent after Cydrome closed to work on the second-generation Titan
and the desktop Stiletto version
- merged with Stellar to form
Stardent
Convex
- C1 - Steve Wallach, Tom Jones
- C2 -
- T. Jones, "Engineering Design of the Convex C2,"
IEEE Computer, January 1989, pp. 36-44. [half page on staffing issues]
Scientific Computer Systems
Stardent
Supertek
- S-1 - (there was a COMPCON paper) - Mike Fang
- acquired by Cray and the S-1 was relabelled as Cray XMS;
the Supertek S-2 design became the Cray YMP-EL
Stellar
- GS-1000, 1988
- OS and compiler team
- Clem Cole was original OS leader
- others included Lee Cooprider, Max Smith, Tom Teixeira,
Les Crudele, Pete Darnell
- Logic designers and chip implementers
- Bill Poduska, Michael Sporer, Todd Basche, Peter Oppen,
and Brian Apgar
- 4-way multithreading with dual-issue from each stream
- M. Sporer, F. Moss, and C. Mathias, "An introduction to the
architecture of the Stellar graphics supercomputer," COMPCON 1988,
pp. 464-467.
- merged with Ardent to form
Stardent
... more to do!
Cal Data
- Cal Data 135, 197x - Ken Omohundro
- microprogrammable, came with PDP-11/40 emulator
- ... material to add ...
Data General
-
DG Nova, 1969 - Henry Burkhardt III
- The Nova was the first 16-bit small computer to use a multi-register
architecture, with 4 registers, 2 of which could be used as index
registers. It had a symmetric instruction set, a clean IO structure and
occupied 5 1/4" in a 19" rack configuration. In 1969, its list price was
about $7,000 with an 8Kb memory.
- DG Nova 2 - Dave Bernstein and Mike Druke
- DG Nova 3 - Dave Bernstein
- DG Nova 4 - Dave Grondalski
- DG Supernova - Larry Seligman and Ron Gruner (first minicomputer to
use solid state memory)
- DG microNova - Gardner Hendrie
- DG microNova 200 - Dave Bernstein (a bit-slice implementation of the
Nova instruction set crammed into the microNova PCB form factor)
- DG Nova 1200 - Ron Gruner
- DG Nova 800 - Larry Seligman
- DG Eclipse
- Ron Gruner - architect, logic design
- Carl Alsing - instruction set design and firmware implementation
- DG microEclipse - Dave Bernstein (an implementation using a two-level
control store to work around the package pinout limitations of the day)
- DG FHP (Fountainhead Project) - Ron Gruner, Rich Belgard,
Dick Bratt, Gerry Clancy, Tom Jones, Larry Katz, and others
(was not marketed; this was the North Carolina-based project
described in Tracy Kidder's book;
see US Patent 4,455,602 "Digital Data Processing System")
- Data General MV 8000
- Tom West - project director and visionary
- Steve Wallach - architect, hardware system layout
- Carl Alsing - instruction set design, hiring
- "Microkids"
- Carl Alsing - manager of microprogramming and simulation
- microcode - Chuck Holland (supervisor), Bob Beauchamp, Jon Blau,
Dave Keating, Paul Reilly, Betty Shanahan, and Steve Staudahler
- simulation - Dave Peck (supervisor) and Neal Firth
- "Hardy Boys"
- Ed Rasala - manager of hardware design
- Ken Holberger (supervisor), Dick Coyle, Dave Epstein, Jim Guyer,
Mike Hobbs, Josh Rosen, Jim Veres, Len Winmill, David Zeek,
Mike Ziegler
- The project is described in Tracy Kidder's book, The Soul of a
New Machine. Tom West, although aloof with the Hardyboys and
Microkids, leaving them for his 'Lieutenants' to manage, worked
closely with Wallach, who designed the system architecture,
Rasala, who designed the logic, and Alsing, who designed the
instruction set and recruited the 'kids'. Tom was the architect
in the sense of mastermind: visionary, leader, and project manager,
who sees the big picture while tracking even the obscure tasks.
- Kidder-book-related resources
- Donald Christiansen,
"All in a Day's Work," Today's Engineer, Feb. 2005.
[brief summary of book]
- John Faughnan and Sanja Stevanovic,
"Flight of the Eagle: The Birthing and Life of a Super-Minicomputer"
(pdf file), project management review, March 1996. [includes MV 8000
project timeline in attachments]
- Evan Ratliff,
"O, Engineers!" Wired, Dec. 2000. [retrospective]
-
where are they now?, Wired, Dec. 2000.
- MV 8000 technical resources
- Jonathan Blau, Charles Holland, and David Keating,
"The micro-architecture of the ECLIPSE MV/8000: Conception
and implementation" (ACM DL link), MICRO-13, 1980.
- David Epstein,
"The ECLIPSE MV/8000 microsequencer" (ACM DL link),
MICRO-13, 1980.
- Neal Firth,
"The role of software tools in the development of the ECLIPSE
MV/8000 microcode" (ACM DL link), MICRO-13, 1980.
- Paul Reilly, Elizabeth Shanahan, and Steven Staudaher,
"An implementation of microdiagnostics on the ECLIPSE MV/8000"
(ACM DL link), MICRO-13, 1980.
- see also
- Data General MV 10000
Digital Equipment Corporation (DEC)
- C. Gordon Bell, J. Craig Mudge, and John E. McNamara,
Computer Engineering: A DEC View of Hardware Systems Design,
Digital Press, 1978, for a wonderful history of DEC systems
- 18-bit computer family
- PDP-1, 1960 - Ben Gurley (head), Harlan Anderson, Dick Best,
Ken Olsen, Stan Olsen, and Bob Savell; influenced by MIT TX-0
- PDP-4, 1962 - Gordon Bell; influenced by MIT LINC
- PDP-7, 1964
- PDP-9, 1968
- PDP-15, 1970
- PDP-2 name reserved for a 24-bit computer which was never built
- 36-bit computer family
- PDP-3, 1960 - paper design, one built by a customer
(Scientific Engineering Institute)
- PDP-6, 1964 - Gordon Bell (architect)
PDP-6 development team:
- Harlan Anderson, VP of Engineering
- Gordon Bell, System Architect
- Alan Kotok, Asst. Architect and Logic Designer
- Russ Doane, Circuits
- Ken Senior(?), Field Service
- Bob Reed, Technician
- Leo Gossel, Diagnostics
- Dit Morse, Software Project Leader
- Tom Hastings and Dave Gross, Monitor
- Harris Hyman and Steve Pinar, MACRO
- Tom Eggers, DDT
- Bell Segal, Utilities
- Peter Sampson and Al Blackington, FORTRAN
- Ed Yourdon, LOADER
-
picture of "PDP-6 Design Team"
- PDP-10 (KA10), 1967 - Alan Kotok (architect)
KA teams, 1967
- Hardware: Alan Kotok, Bob Clements, Dave Gross, and
Bill English (documentation)
- Software: Tom Hastings, Tony Wachs, Dave Plummer, Don Whitcraft,
Alan Frantz, Pat White, Valdeane Alusic, Penny Land, Mauri Fredrickson,
Joe Fries, Nick Pappas, Tom Eliot (documentation), and
Chris White (joined in 1969)
- KI10 (1060), 1972
- KL10 (1080), 1976
- Alan Kotok (architect and largely responsible for cache and memory
design), Bob Reid (execution unit), Jud Leonard (designed the
"business instruction set" and wrote the microcode), Bill Bruckert
- also used in DECSYSTEM-20 (2040/2050)
- derivatives named with A,B,C,D,E suffixes
- KS10, 1978
- also used in DECSYSTEM-20 (2020)
- KC10 (Jupiter) cancelled
- some other web sites
- 12-bit computer family
- PDP-5, 1963 - Gordon Bell and Alan Kotok; Edson DeCastro did the
logic design; influenced by the MIT LINC
- PDP-8, 1965
- PDP-12 - switched between PDP-8 and LINC instruction sets
- PDP-14
- 16-bit PDP-X (cancelled) - Edson DeCastro and Henry Burkhardt;
register-memory model like PDP-10
(see
Bob Supnik, "What was the PDP-X?", 2004, pdf)
- 16-bit computer family, PDP-11 - Gordon Bell
- PDP-11/20, 1970
- PDP-11/05, 1972
- PDP-11/45, 1972
- PDP-11/70, 1975
- LSI-11, 1975
- F-11, 1979
- J-11, 1983
-
G. Bell and W. Strecker, "What have we learned from the PDP-11?
(1975)
-
G. Bell, Retrospective on the PDP-11 (1995, unpublished)
-
G. Bell and W. Strecker, Retrospective on the PDP-11 (1995)
- 32-bit computer family, VAX - William Strecker
- VAXA group met in 1975, composed of Gordon Bell, Peter Conklin,
Dave Cutler, Bill Demmer, Tom Hastings, Richie Lary, Dave Rodgers,
Steve Rothman, and Bill Strecker as chief architect
- "Blue Ribbon" committee to simplify design in 1976:
three hardware engineers, Bill Strecker, Richie Lary,
and Steve Rothman; and three software engineers, Dave
Cutler, Dick Hustvedt, and Peter Lipman
- TTL-based implementations
- VAX-11/780, 1978 (5 MHz, TTL)
- Dave Rodgers (engineering manager)
- Bob Stewart (cache), Al Helenius (instruction decoder),
Steve Jenkins (execution unit)
- Jud Leonard (microcode group leader), group included
Tryggve Fossum, Marty Hurley, and others
- VAX-11/750, 1980 (gate array TTL) - David Cane
- VAX-11/730, 1982 (bit-slice)
- Ken Okin (project lead manager)
- Stan Lackey (processor hardware designer, responsible for
the implementation architecture and logic design)
- microcode: Simon Steely (supervisor),
Jim Van Sciver (floating-point),
Tim Leonard (interrupts and exceptions, memory management,
privileged instructions, and compatibility mode),
Kim Meinerth, and Dave Miller.
- hardware engineers: Dave Stoner, Dave Hiles, Dave Ives,
and Dave Thomson
- VMS support for the 730: Trudy Matthews and Nancy Kronenberg
- Nancy Kronenberg was Mary Payne's daughter, and they may have been
Digital's first two female consultant engineers. Mary was a
mathematician, was the source of the VAX POLY instructions, drove
the "good to the last bit" policy for VAX floating-point accuracy,
and was Digital's representative to the IEEE FP standards committee.
- Roger Gourd was the engineering manager for VAX Software;
Dave Cutler and Dick Hustvedt were VMS co-designers
- first dual VAX was put together by Goble at Purdue, 1980
- ECL-based implementations
- 8600, 1984 (12.5 MHz) -
- Jud Leonard (system architect until 1981)
- Tryggve Fossum led the floating point work,
Al Helenius did the instruction decoder, and
Bob Elkind designed the execution unit
- first VAX design with overlapped operand decoding and fetching;
see DTJ August 1985
- 8800/8700/8500, 1986
- pipelined the microinstructions
- I-box and E-box - Jim Keller, project leader
- FPU - John Zurawski and Anil Jain
- see DTJ February 1987
- 9000, 1989 (code named Aquarius, 62.5 MHz) -
"mainframe" VAX with vector processing
- design started in 1983; RISC-like load/store architecture
within the E-box; the I-box acted as a preprocessor and
translated VAX instructions into simpler internal instructions
for the E-box as well as decoded and fetched operands
- original team members - David Fite, Tryggve Fossum, Bill Grundmann,
Rick Hetherington, Dwight Manley, John Murray, Bill Smith, and
David Webb
- I-box - John Murray, project leader;
David Fite, branch prediction, inst. fetch, inst. decode;
Mark Firstenberg and Mike McKeon
- E-box - Ron Salett, project leader;
Bill Grundmann, Larry Herman, Ginny Lamere, Elaine Fite,
Dan Sterling, Eileen Samberg, Mark Haq, and Matt Adiletta
- M-box - Dave Webb, Maurice Steinman, Joe Macri, Brad Hollister,
and Basheer Ahmed
- V-box - Dileep Bhandarkar, chief architect for vector processing;
Francis McKeen, project leader; Richard Brunner, Bimal Patil,
William Rodgers, and Greg Yoder
- service processor - Michael Evans, project leader; Karen Benard,
Stephen Conway, David D'Antonio, Susan DesMarais, Matthew Goldman,
Paul Leveille, and Brian Rost
- TLB and cache design - Rick Hetherington, project leader
- performance modeling - Dwight Manley
- see DTJ Fall 1990
- other mid-range ECL projects, ultimately cancelled due to the
progress in CMOS clock rate, were BVAX, Argonaut, and Raven
- NMOS-based implementations
- microVAX, 1985 (VAX subset)
- microVAX I was a quick implementation (NMOS datapath and TTL control
unit) by Dave Cutler's group in Seattle to test a subset approach
to implementing the VAX instruction set
- microVAX II was a 5 MHz single-chip CPU implementation with major
parts of the CPU design and microcode taken from the V-11 project
- Bob Supnik (CPU project manager and microcode),
Dan Dobberpuhl (CPU lead engineer),
Rich Witek (CPU microarchuitecture),
Larry Walker (FPU project manager), and
Bob Simcoe (FPU lead engineer)
- see DTJ March 1986 and
Bob Supnik's microVAX description
- V-11, 1986 (code named Scorpio, up to 6.25 MHz)
- chipset implementing the full VAX instruction set, used in 8200
- project started earlier than the microVAX II but shipped after
the microVAX II
- Bill Johnson (project manager),
Dick Sites (chief architect and project lead for microcode team),
Ed Burdick (IE chip project lead),
Bill Grundmann (project lead M chip)
- see
Bob Supnik's v11 description
- CMOS-based implementations
- CVAX, 1987 (up to 14 MHz)
- chipset used in VAX 6200/6300
- Dan Casaletto (project manager),
Bob Supnik (chief architect and most of microcode)
Paul Rubinfeld (CPU chip project lead),
Gil Wolrich (FPU chip project lead)
- see DTJ August 1988 and
Bob Supnik's CVAX description
- Rigel, 1989 (up to 40 MHz)
- chipset used in VAX 6400/4300
- Amnon Fischer (project manager),
Mike Uhler (chief architect and most of microcode),
Bill Herrick (CPU chip project lead),
Moshe Gavrielov (FPU chip project lead),
Rebecca Stamm (cache controller chip project lead)
- see DTJ Spring 1990 and
Bob Supnik's Rigel description
- NVAX, 1991 (up to 90 MHz) and NVAX+, 1991 (up to 143 MHz)
- single chip, based on microarchitecture of VAX 9000
- NVAX used in VAX 6600 and various 4x00 models;
NVAX+ used in VAX 7600/10600
- Bill Herrick (project manager), Michael Uhler (chief architect),
Debra Bernstein, Larry Biro, John Brown, John Edmondson,
Jeffrey Pickholtz, and Rebecca Stamm
- see DTJ Summer 1992 and
Bob Supnik's NVAX description
- VAX development ended in 1996
- See the booklet
VAX OpenVMS at 20, 1977-1997 (includes a picture of the 8600 design team)
- PRISM, Alpha - see DEC entry in workstation section
- Mica (high performance video chip) - John Kowaleski
National Semi
Prime
- Bill Poduska, founder;
architecture derived from Honeywell 16-bit computers with
influence also from Multics (e.g., protection rings);
first architects were Walter Jones, who went on to IPL to design
a 3090 ECL based machine, Paul Jones, who went to Stellar,
and Mike Sporer.
Bill Poduska went on to start up Apollo.
- Prime 950 series - Paul Rodman and Dave Papworth
Tandem
- Tandem T16 - Michael Green, Joel Bartlett, Jim Katzman, etc.
... much more to do!
Intel
- 8008, 1973
- 8080, 1974
- 8085
- S.P. Morse, B.W. Ravenel, S. Mazor, and W.B. Pohlman,
"Intel Microprocessors -- 8008 to 8086,"
IEEE Computer, October 1980, pp. 42-60.
From the acknowledgements section:
Pany people played significant roles in the development of these
processors. Hence, it is not possible to single out a few for all the
credit. However, if forced to choose those people who played the most
significant roles on each chip, we can name the following: M.E. (Ted)
Hoff was the architect and Federico Faggin the chip designer of the
4004. Stanley Mazor contributed to the 4004 architecture as well as to
the architectures of the 8008 and 8080. Hoff and Hal Feeney were the
major contributors to the 8008 development. Faggin managed the
development of the 8080 and participated in defining its architecture,
with Masatoshi Shima doing the logic and circuit design. Roger Swanson
defined the new instructions for the 8085 while Peter Stoll and Andrew
Volk performed the 8085 logic and circuit design. The 8086 architecture
was defined by Stephen Morse and refined by Bruce Ravenel, with James
McKevitt and John Bayliss responsible for the logic and circuit design.
William Polhman managed both the 8085 and 8086 activities.
Motorola
- 6800, 1974 - Mike Wiles did the original architecture (original
management goal was a single-chip PDP-11 microcomputer)
- 6809, 1979 - Terry Ritter and Joel Boney (see the articles on
the 6809 in BYTE, January and February, 1979, with pictures of
the design team)
MOS Technologies
Zilog
Includes 32-bit and 64-bit processors. Some of these were called
supermicrocomputers in the 1980s.
Apple/IBM/Motorola PowerPC
-
PowerPC - Rich Oehler (IBM, with Cathy May and Ed Silha),
Keith Diefendorff (with Motorola at the time), Ron Hochsprung (Apple),
and John Sell (with Apple at the time)
- 32-bit implementations
- 601, 1993 - Charles Moore and John Muhich
- 602, 1995
- 603 family
- 603, 1993 - Brad Burgess, Russ Reininger, and Jim Kahle
- 603e, 1995 - Brad Burgess and Robert Golla
- 604 family
- 740/750 (G3), 1997 - Brad Burgess
- microarchitecture similar to 603
- 7400/7410 (G4), 1999 - Mike Snyder
- basically a 750 with Altivec
- 7450, 2001 - Brad Burgess (chief) and Tom Peterson (memory system)
- 64-bit implementations
- 620, 1995 - Chin-Cheng Kau, Dave Levitan, Paul Rossbach,
Roger Bailey, Don Waldecker, and Dave Bearden
- shipped late, first MP-enabled PowerPC chip
- Power3 (630), 1998 - Larry Thatcher, Paul Harvey, Mike Mayfield,
and H. Lee; Mark Papermaster was the manager.
- started with PowerPC 620 design
- Power4, 2002 - Jim Kahle and Chuck Moore
- two cores per chip
- see
"IBM icon of progress: Power 4"
- Carl Anderson, Harold Chase, and James Warnock - circuit design,
tools, methodology, manufacturing, and I/O subsystem
- Roch Archambault, Robert Blainey, and James McInnes -
compiler technologies
- Ravi Arimilli and Leo Clark - multi-core,
integrated and distributed cache, and memory
- Geoffrey Blandy, Hye-Young McCreary, and Bruce Mealey - AIX
- Bing-Lun Chu, Steve Fields, and Kevin Reick - design,
verification, instrumentation, and test technologies
- Jim Kahle and Hung Le - superscalar,
superspeculative, out-of-order, high frequency core
- Jan Klockow, Bradley McCredie, Michael Nealon, and Edward Seminaro -
system design, power, packaging, and cooling technologies
- Chet Mehta and David Willoughby - firmware
- PowerPC 970 (G5), 2003 - Peter Sandon (chief)
- derivative of Power4 but with single core and Altivec added
- Power5 - Ravi Arimilli (?)
- Power6 - Balaram Sinharoy (?), Brad McCredie
- extensions for AS/400 -
Andy Wottreng and Mike Corrigan (under Frank Soltis)
- called PowerPC AS, now called iSeries
- some chips designated as RS64 are used in RS/6000 models
- PPC AS A30 (Muskie), 1995
- PPC AS A10 (Cobra), 1995 - at Endicott
- PPC AS A35 (Apache, RS64-I)
- Star family, 2-way multithreaded
- Northstar (PPC AS A50, RS64-II), 1998
- Pulsar (RS64-III), 1999
- IStar, 2000
- SStar (RS64-IV), 2001
- Power4 includes AS extensions
AMD 29K (Advanced Micro Devices)
- AMD 29000
- Brian Case and Ole Moller (initial contributors);
also Gigy Baror, Philip Frieden, Smeeta Gupta,
Mike Johnson, Cheng-Gang Kong, Tim Olson, and David Sorensen;
managerial support from Paul Chu and Bill Harmon
- 29000, 1987 - David Witt
- 3 bus, integer only, no d-cache, i-cache
was a branch target cache (the BTC held the first four instructions
at branch targets to cover the latency of fetching instructions
from memory, idea for this came from Phil Frieden)
- 29005 - cost-reduced 3-bus 29000, missing the BTC and MMU
- 29027 (FPU), 1987 - Tim Flaherty and Bob Perlman
- 29050, 1990 - Bob Perlman (lead), Mike Johnson, and Tim Olson
- included 29000 and 29027, but was more than just an integration
- unreleased superscalar 29K processor - Mike Johnson
- was described at 1994 Microprocessor Forum and then leveraged as
the core of the AMD K5
- 29030/29035/29040
(see embedded processor section)
- See also
Johnson, Mike (William Michael) oral history,
Kevin Krewell (Interviewer), May 9, 2014
Apollo
- Bill Poduska and Dave Nelson architected the packet-plexor domain
network which became Apollo.
- DN3000
- PRISM (3-wide LIW), 1988 - Barry Flahive, Rick Bahr, and John Yates
- John Yates contributed the multi-issue idea. An "FP companion" bit
is the leftmost bit of the integer instruction format and is used to
indicate if a paired floating-point instruction follows (which will
be issued in parallel). The integer/FP pair must start on an 8-byte
boundary, and an FP instruction cannot appear without the paired
integer instruction. The five-operand version of the FP instruction
format can specify both a multiply and an independent add/sub/truncate.
Thus, with the integer operation, the Apollo can execute a peak of
three operations/cycle -- FP multiply, FP add, and an integer
operation (typically a load, for instance, of two floating point
registers). The design was perfectly balanced for single-precision
Linpack or FFT.
- DN10000 - the first (and last) model, 54 MIPS, 36 megaflops in 1989.
- Paul Mageau and Andy Milia were chiefly responsible for the
memory system. Doug Voorhies, Olin Lathrop, and Dave Kirk
were chiefly responsible for the graphics system.
DEC (later Compaq)
- Titan, 1986 - Neil Wilhelm and Jud Leonard
- MultiTitan, 1988 - (DEC WRL) Norm Jouppi, +
- PRISM (Parallel Reduced Instruction Set Machine), 1989 - Dave Cutler,
Dileep Bhandarkar, Rich Witek, Dave Orbits, and Wayne Cardoza
- multiple RISC efforts within DEC
- Titan, started in 1982 under Forest Baskett
- SAFE (Streamlined Architecture for Fast Execution), started in 1983 -
Alan Kotok and Dave Orbits
- HR-32, started in 1984 - Rich Witek and Dan Dobberpuhl
- CASCADE project started under Dave Cutler in Seattle in 1984
- Cutler tasked in 1985 to define corporate RISC plan
- see Dileep Bhandarkar, section 1.4, Alpha Implementations and
Architecture, Digital Press, 1996
- first draft of PRISM architecture in August 1985
- PRISM was initially a 64-bit architecture and had vector instructions;
also included the idea of Epicode, which developed into PALcode on
the Alpha
- 32-bit address version developed as well for single-chip implementation
- Cutler went to Microsoft after DEC cancelled the project in 1988
- Bhandarkar published COMPCON '90 article in which it was called the
"R.I.P." architecture; see also section 1.5, Alpha Implementations and
Architecture, Digital Press, 1996
- PRISM integer unit chip - Robert Conrad, et al., ISSCC 1989
- microPRISM - Rich Witek (lead microarchitect)
- Alpha - Dick Sites and Rich Witek
- task force for extending VAX and VMS in 1988;
Alpha design started in 1989
-
Richard Sites, Alpha AXP Architecture, Digital Technical Journal, Vol
4 No 4, 1992
- a case history of developing the architecture was written up by
R. Comerford, "How DEC developed Alpha," IEEE Spectrum, July 1992,
pp. 26-31.
-
Dick Sites and Dirk Meyer, Alpha architecture video, April 1992
-
Allen Baum, Evolution of the Alpha (video), November 2000
- implementations
-
21064 (EV4), 1992 - Rich Witek (lead)
-
21164 (EV5), 1995 - John Edmondson (lead during design), Pete Bannon,
and Jim Keller (lead during advanced development)
- 21164PC, 1997 - Pete Bannon (lead)
- 21264 (EV6), 1998 - Jim Keller (lead)
- 21364 (EV7), 2003 - Pete Bannon, ...
- 21464 (EV8) - cancelled
- Joel Emer gave overview at PACT 2001
- The cover art for the February 1993 special issue of CACM on
"Digital's Alpha Chip Project" depicts the DEC Alpha as a 1967
FIA endurance racing Gulf Mirage M1 [a lightweight version of
the Ford GT40, built by John Wyer's team] as incongruously drag
racing. Two years later, Dick Sites wrote that he'd like to see
Alpha thought of as an express-delivery truck -- fast but
"commonplace" -- rather than as a race car -- which is "blazingly
fast, but not seen in your own neighborhood".
[Digital Tech. Jrnl., special 10th anniv. issue, 1995, pp. 5-6]
- Apr. 27, 1997 - excerpt from BusinessWeek article on
"Why The Fastest Chip Didn't Win":
But even before Alpha hit the market, Digital fumbled. The company had
shown off early versions of the chip at an industry conference in February,
1991, and engineers at Apple Computer Inc. were impressed. Apple was in
the market for a new chip supplier, and Alpha looked promising.
In late June, John Sculley, then Apple's CEO, invited Kenneth H. Olsen,
Digital's founder and president, to dinner. Sculley had a proposition: Apple's
Macintosh computers were starting to run out of gas, and he wanted to do a
complete redesign with Alpha at the heart of the new Macs.
But Olsen had doubts about Alpha. His unshakable faith in the VAX
computer, which had turned Digital into IBM's most formidable competitor in
the 1980s, made him reluctant to phase it out too soon in favor of Alpha.
Olsen asked a team of Digital's top engineers to extend the computer's
design for another generation--and he rejected Sculley's proposal.
A few months later, Apple announced that its new Macs would run on the
PowerPC chip, a competing design by IBM and Motorola Inc. Sculley says
one Digital director later told him that Digital's board was ''distressed that
nothing came of these discussions and that Digital lost a great opportunity.''
The Alpha faction at Digital was crestfallen. ''Ken did not want the future of
the company riding on Alpha,'' says William R. Demmer, a former
vice-president of Digital's Alpha and VAX businesses who retired in 1995.
- Jan. 26, 1998 - Compaq
announces plans to buy DEC
- June 25, 2001 - Compaq cancels EV8 in order to consolidate on
Itanium, and sends design team to Intel;
PR release states
"In one bold stroke, Compaq is extending its 10 years of leadership
in 64-bit computing for the next decade and beyond."
- Sept. 4, 2001 - HP and Compaq
announce merger plans
HP
- HP PA-RISC 1.0 - Bill Worley (lab manager) and Michael Mahon (head of
architecture team)
- first called "Spectrum" and started by Joel Birnbaum
- original team members: Allen Baum,
Hans Jeans, Russell Kao, Ruby Lee, Michael Mahon, Terrence Miller,
Steve Muchnick, and Bill Worley; later David Fotland
- Terrence Miller - compiler mgr.; Steve Boettner - OS mgr.;
Mike Gardner - hardware design mgr.; Fred Luiz - I/O mgr.; Tony Lukes -
perf. analysis mgr.; Dan Magenheimer - simulator;
Russell Kao - prototype;
Craig Hansen - FP architecture
-
Michael Mahon, HP PA-RISC video, June 1987
-
Michael Mahon, PA-RISC Design Issues video, April 1992
- see the feature article at HPL on
"Bill Worley: A Computer Architecture Wizard"
- implementations
- HP 3000/840 - team led by David Fotland
- ...
- PA-RISC 1.1
- Michael Mahon and Jerry Huck
- MAX-2 multi-media instructions - Ruby Lee
- implementations
- PA 7000, 1989 - team
- PA 7100 (superscalar), 1992 - team
- PA 7100LC (superscalar, on-chip 1K icache), 1994 - team
- PA 7200 (superscalar, 2K on-chip dcache), 1994 - team
led by David Fotland
- PA 7300LC (superscalar, dual 64K on-chip caches), 1996 - team
- PA-RISC 2.0 - Michael Mahon and Jerry Huck
- implementations
- PA 8000 (superscalar), 1996 - team
- PA 8200 (superscalar), 1997 - team
-
PA 8500 (superscalar, 1M + 512K on-chip caches), 1998 - team
- PA 8600, 2000
- PA 8700, 2001
- PA 8800 - dual 8700 cores
- from
Joel Birnbaum's talk at 1997 Microprocessor Forum:
"In the architecture stage, all of our work has always been done with teams,
including hardware, software, and technology experts, often sitting
side-by-side. At the heart of our principles is the synergy between the
compiler and the hardware, with the compiler relied upon to help avoid
hardware bottlenecks and critical paths, and the architectural hardware
mechanisms developed to reduce stalls, delays, and critical paths in the code."
Intergraph
- Intergraph Clipper
- C100, 1985 - Howard Sachs, Walt Hollingsworth, and James Cho
- C300, 1987 -
- C400 (superscalar), 1991 -
- C5 - Howard Sachs and Siamak Arya
- work abandoned in 1993
IBM
- 801
- Joel Birnbaum started a project in early 1975 within the
Research Division of IBM to do a machine based on John Cocke's ideas
for a simple machine: load-store architecture, execute (delayed)
branches, and split cache;
the project took on the 801 name because the T.J. Watson
Research Center building number is 801
- John Cocke and Marty Hopkins worked on the early definition which had
two- and four-byte ops and 16 GPRs
- George Radin became manager afer Joel Birnbaum was named director
of the Computer Science Dept.
- Hardware team: Frank Carrubba (manager), Paul Stuckert, Norman Kreitzer,
Richard Freitas, and Kenneth Case
- Compiler team: Marty Hopkins (manager), Richard Goldberg, Peter Oden,
Philip Owens, Peter Markstein, and Greg Chaitin
- OS team: Richard Oehler (manager) and Albert Chang
- Bill Worley contributed significantly through the years
- Marty Hopkins:
Ideas came from many sources and a lot of things
were tried that didn't pan out. Examples were doing all protection
in software and data base memory. We also started our own programming
language, pl.8, which had an optimizing compiler. We invented the
idea of doing register allocation by graph coloring. Greg Chaitin
was the leader but I sometimes think that half the lab contributed
ideas. The one problem Greg couldn't solve in a clean fashion was
spilling when there were too few registers. I decided to see what
a 32 register machine would look like. This led to all four byte ops
which in turn made for a more regular machine and thus a faster cycle
time. This is only one example of how software and hardware
considerations were treated equally to get something better.
"The [final] instruction formats were the same that I
first drew up to accommodate 32 registers. The general flavor of
decision making was collegial and informal. We also had a great crew
who worked with us outside of Research. Phil Hester of IBM in Austin
adopted the old 16 register machine which became Romp (RT/PC). Later
on Austin did the RS/6000 with us. This was based on a Research
variant called America. I can't begin to list all the people who
contributed. Further ripples went out to PowerPC with Apple and
Motorola as well as the AS/400 version of RS/6000. There were many
variations that never saw the light of day."
- M. Hopkins, "A Perspective on the 801/Reduced Instruction Set Computer,"
IBM Systems Journal, vol. 26, no. 1, 1987, pp. 107-121.
- G. Radin, "The 801 minicomputer," Proc. ASPLOS-I, Palo Alto,
March 1982, pp. 39-47.
- IBM America / Power - John Cocke, Greg Grohoski, Rich Oehler
- arose from ideas of
- original America team (1985): Greg Grohoski (lead),
Marc Auslander, Al Chang, Marty Hopkins, Peter Markstein,
Vicky Markstein, Mark Mergen, Bob Montoye, and Dan Prener
- quote from IBM interview with John Cocke:
Trimble: I know that many people from IBM Research went to
Austin to make the RS/6000 happen. Who were some of the players
from Research?
Cocke: Well, of course Andy Heller worked very hard on that
project. He had been a very vocal proponent of RISC from day one.
Al Chang contributed many, many ideas in both hardware and
operating system software. In the compiler area, Peter Markstein
was a source of many novel ideas, and Greg Chaitin wrote the
compiler register allocator. Then there were Greg Grohoski, who did
the timer work, and Fred Blount who did a lot of the overall planning.
- quote from team member
Greg Grohoski was a right hand man to John. [John] would call
[Greg] at 1-2am to talk about the ideas. Though John had many
ideas and every day, realization of those ideas would not have
been possible had it not been [for the] cool analytical mind of
Greg who listened to John patiently and synthesized them into reality.
-
Phil Hester, RS/6000 video, Aug. 1990
- first commercial use of register renaming - see U.S. Patent 4,992,938,
John Cocke, Gregory Grohoski, and Vojin Oklobdzija, "Instruction control
mechanism for a computing system with register renaming, map table and
queues indicating available registers" (February 12, 1991)
- implementations
- RIOS, 1989 - Greg Grohoski
- America with IEEE floating point
- icache and branch processing - Charles Moore (lead),
Ed Broufarah, and C.C. Lee
- integer (fixed-point) unit - Jim Kahle (lead), Larry Thatcher, Dennis
Gregoire, Paul Harvey, and Brian Bakoglu
- floating-point unit - Myhong Nguyenphu (lead), Daniel Cocanougher,
Richard Fry, Pat Mills, Oscar Mitchell, and Troy Hicks
- RSC, 1992 - Charles Moore?
-
Power2 - Greg Grohoski, Warren Maule, Larry Thatcher,
and a few others
- P2SC, 1997
- switch made to 64-bit PowerPC architecture
(see also Apple/IBM/Motorola PowerPC above)
Intel
- Intel iAPX 432 - Justin Rattner (chief), Roger Swanson, and George Cox
- others involved include Kevin Kahn, Fred Pollack, Dan Hammerstrom,
and Konrad Lai
- implementation - (Steve Domenik ?)
- an ambitious but ultimately unsuccessful design that has been used
to (unnecessarily, IMHO) discredit capability-based processor design
- see the excellent post mortems:
- Bob Colwell, Ed Gehringer, and Doug Jensen,
"Performance Effects of Architectural Complexity in the Intel 432,"
ACM Trans. on Computer Systems, vol. 6, no. 3, August 1988,
pp. 296-339.
- Ed Gehringer and Bob Colwell,
"Fast Object-Oriented Procedure Calls: Lessons From the Intel 432,"
ISCA-13, Tokyo, 1986, pp. 92-101.
- also -
selected April 1995 comp.arch traffic discussing the 432
- (would be interesting to compare "capability-induced slowdown"
between native IBM Power2 vs. IBM AS/400-PPC)
- see
Eric Smith's list of papers on the 432
- i860 (see VLIW processor section)
- i960 (see embedded processor section)
- 386, 486, Pentium, Pentium Pro, etc. (because of market presence,
see Wintel processor section)
- IA64 / Itanium
(see independence arch. processor section)
MIPS
- MIPS-I, 1986 - Craig Hansen, chief architect
- much influenced by Stanford MIPS - John Hennessy
- team members:
- John Hennessy, Larry Weber, and Fred Chow (compilers and
related ISA issues)
- John Mashey, Mike Demoney, and Steve Stone (OS-related issues,
e.g., MMU, interrupts)
- Steve Przybylski (cache issues)
- Chris Rowen, John Moussouris, and Skip Stritter
- MIPS-II, 1990 - Craig Hansen, chief architect
- with many suggestions made by Earl Killian, George Taylor, and others
- MIPS-III (64-bit arch.), 1991 - Earl Killian, chief architect
- John Hennessy was the impetus for MIPS III and
suggested some of the ways in which it could be done.
- MIPS-IV - Peter Hsu
- started at SGI before the SGI/MIPS merger, although they consulted
with MIPS.
- MIPS-V (many FP opts.), 1995 -
Earl Killian finalized it as the chief architect; contributions
by Bill Huffman and Peter Hsu
- MDMX, 1996 - the Digital Media ASE (Application Specific Extension)
- The impetus for this came from Tim Van Hook and Henry Moreton within
SGI. Peter Hsu participated. Several people, including Iain
McClatchie and Catharine Van Ingen helped create the first
architecture documents for it.
- MIPS-V (FP paired-singles), 1996 -
- implementations
- R2000, 1986 - Craig Hansen, Ed Hudson, John Moussouris, Tom Riordan,
Chris Rowen, and Dan Freitas
- R2010 (FPU), 1986 - Craig Hansen, Ed Hudson, Mark Johnson, and others
- R3000, 1988 - Craig Hansen, Tom Riordan and Ed Hudson
- R3010 (FPU), 1988 - essentially identical to R2010
- R6000, 1989 - George Taylor; other people involved
were Mike Farmwald and Allen Roberts
- R4000/4400, 1992 -
Peter Davies, Ed Hudson, Earl Killian, and Tom Riordan
(the design grew out of debates between Ed Hudson and Tom Riordan, with
Peter Davies and Earl Killian serving as the referees)
- "superpipelined" impl. of MIPS-IV - 8-stage pipeline
- R8000 (TFP), 1994 - Peter Hsu (lead)
- an SGI project that was folded into the MIPS product line
(e.g., compare the different fused-multiply-add definitions
on the R8000 and the R10000)
- There is a direct connection of the basic ideas of
the Cydrome Cydra 5 and the R8000. Very different
implementations but the basic ideas were the same.
- Cydra folks: Peter Hsu, Ross Towle, John Brennan,
Jim Dehnert (and Joe Bratt joined later);
Multiflow folks: Paul Rodman and John Ruttenberg
-
Peter Hsu, SGI TFP video (Hot Chips V), August 1993
- R10000, 1996 - Chris Rowen and Ken Yeager
- R12000, 1998
- R4200/4300, 1993 -
- R4600/4700, 1994 - Earl Killian and Tom Riordan
- R5000, 1996 - Earl Killian and Tom Riordan
- QED RM7000, 1997 - Tom Riordan
Motorola 68K/88K
- 68000, 1979 - Skip Stritter (lead architect), John Zolnowsky, and
Tom Gunter (design manager)
- Skip Stritter and David Leitch began the instruction set definition,
and John Zolnowsky did most of the detailed work. The instruction
set design was based heavily on Len Shustek's PhD thesis. Len, Skip,
and John had worked together on their PhDs at Stanford (all under
Forest Baskett?).
- logic design and microcode - Nick Tredennick
- bus controller - Tom Gunter
- bus protocol and TTL breadboard - Les Crudele
- circuit design - Doyle McAlister and Richard Crisp
- circuit simulation - Mike Spak
- software performance evaluation - Paul Lee
- see E. Stritter and T. Gunter, "A Microprocessor Architecture for a
Changing World: The Motorola 68000," IEEE Computer, Feb. 1979, pp. 43-52.
- Nick Tredennick has written about the design effort in
"Experiences in Commercial VLSI Microprocessor Design,"
Microprocessors and Microsystems, October 1988, pp. 419-432.
- 68881/2 (FPU) - Joel Boney, Van Shahan, Ashok Someshwar (sp?),
and Clay Huntsman
- 68010, 1983 - John Zolnowsky (inst. set extensions) and
Doug MacGregor (microcode)
- 68020, 1985 - Bill Moyer, Dave Mothersole, John Zolnowsky, and
Doug MacGregor (microcode)
- 68030, 1987 - Joel Boney (architecture design manager), Doug MacGregor,
Bill Moyer, and Sharon Lamb (who got things started)
- microcode by Raju Vegesna, microcode assembler by Ed Rupp
- 68040, 1991 - Van Shahan was the main architect
-
68060, 1994 - Joe Circello
- 88100 - Mitch Alsup, Yoav Talgam, Jim Klingshirn, Carl Dobbs,
Janet Sooch
- 88200 CMMU - Mitch Alsup, Elie Haddad, Claude Moughanni,
Jim Klingshirn
- 88400 CMMU - Claude Moughanni, Terry Lawell
- 88110 (2-way superscalar), 1991 - Keith Diefendorff (chief),
Willie Anderson (graphics and FP extensions),
and Bill Moyer (memory system)
- 88120 (abandoned) - Mike Shebanow, ...
National Semiconductor
- National Semiconductor 32K - Dan O'Dowd and Les Kohn
- 32016/16032 - Avraham Menachem (microarchitecture and chip design),
Asher Kaminker (microcode), and Yoav Lavy (BIU, processor buses,
external MMU, and interrupt controller)
- 32332 - Ran Talmudi
- 32532, 1987 - Uri Weiser, Don Alpert, Gigi Licht, Jonathan Levy
(BIU, MMU, and dcache), and Sidi Yom Tov (design manager)
- B. Maytal, S. Iacobovici, D. Alpert, D. Biran, J. Levy, and
S.Y. Tov, "Design Considerations for a General Purpose
Microprocessor," IEEE Computer, January 1989, pp. 66-76.
- D. Alpert, J. Levy, and B. Maytal, "Architecture of the NS32532
Microprocessor," Proceedings ICCD, October 1987, pp. 168-172.
- 32732 (a.k.a. 32764 and Swordfish, superscalar design,
not delivered as N32K family member), 1991 - Don Alpert
(see
Swordfish web page and CompactRISC)
- See also
Oral History Panel on the Development and Promotion
of the National Semiconductor 32000 Microprocessor,
Donald Alpert, Subhash Bal, Robert Freund, Giora Yaron,
and moderated by Richard Sanquini, February 26, 2008,
Computer History Museum.
- (see embedded processor section)
SPARC
- SPARC versions 7/8, 1986/1990 - Robert Garner, chief architect
- much influenced by the UC Berkeley RISC I and RISC II work of
Dave Patterson, Manolis Katevenis, and Bob Sherburne
- started in 1984 when Bill Joy (VP of Sun R&D) brought in Dave Patterson
(Berkeley RISC) as a consultant
-
webcast (Real Player) with Bill Joy discussing history of SPARC
- v7 architecture team members: Robert Garner (chief architect),
Anant Agrawal and Joan Pendleton (hardware),
Steve Kleiman (operating systems),
Steve Muchnick (languages),
David Hough (floating point),
and Bill Joy ("jack of all trades and chief tie-breaker")
- advisors: Faye Briggs, Will Brown, John Gilmore, Dave Goldberg,
Don Jackson, Tom Lyon, Masood Namjoo, Dave Patterson, Wayne Rosing,
K.G. Tan, Richard Tuck, Dave Weaver, and Alex Wu
- Steve Muchnick - compiler manager and in charge of overall performance;
Steve Kleiman - Unix port technical lead; Dock Williams - Unix port;
Will Brown - simulator
- see the summer 1988 special issue of SunTechnology (vol. 1, no. 3) for
"The SPARC Papers". The "/work.group" column (pp. 33-37) describes
the development of the architecture. On p. 33 there is a picture of
the design team around Eric Schmidt's red Ferrari.
(The SPARC papers were also published as a book by Springer-Verlag,
Ben Catanzaro, editor, 1991.)
-
Dave Patterson and Wayne Rosing, SPARC video, June 1989
- in early design meetings Muchnick ruled out a graph coloring register
allocator for the initial compilers, and, following Patterson's
advice, a decision was made that register windows should be included
in the architecture as a way to ensure that operands stayed in
registers; however, by the time the first systems shipped, the Sun
compilers were to a point where better register allocation was a
feasible option [see D. Patterson and C. Sequin, "Retrospective:
RISC I: A Reduced Instruction Set Computer," in G. Sohi (ed.),
25 Years of the International Symposia on Computer Architecture:
Selected Papers, ACM Press, 1998]
- implementations
- 16.67 MHz Fujitsu gate-array, 1986
- IU (MB86900) - Anant Agarwal and Masood Namjoo
- FP control (MB86910, controlled two Weitek data path chips) - Don Jackson
- processor board for Sun 4/200 - Robert Garner and Ed Kelly
- 33 MHz Cypress 7C600, 1990
- IU (CY7C601) -
- FP control (CY7C608, controlled TI FPU chip) -
- Metaflow Lightning/Thunder
- MicroSPARC, 1991 -
- MicroSPARC 2, 1994 -
- TI SuperSPARC (Viking), 1992 - Greg Blanck
- TI SuperSPARC 2, 1995 -
- Ross HyperSPARC, 1993 -
Raju Vegesna (spec) and Jim Monaco (simulator)
- Generation 1: Pinnacle -> Colorado 3 -- Peter Jewett, Greg Gregorio,
Sarangan Padalkar, Haytham Samarchi, Mike Seningen, Sang Yoo
- Pinnacle - 55, 60, 66 MHz versions in Cypress 0.65 micron
- Colorado 1 - 90, 100 MHz versions in Fujitsu 0.50 micron
- Colorado 2 - 125 MHz version in Fujitsu 0.45 micron
- Colorado 3 - 150, 166 MHz versions in Fujitsu 0.40 micron
- Generation 2: Colorado 4 - Colorado 5 (new sequencer and
on-chip data cache) -- Mitch Alsup, Greg Gregorio,
Sarangan Padalkar, Haytham Samarchi
- Colorado 4 - 180, 200 MHz versions in Fujitsu 0.35 micron
- Colorado 5 - 250+ MHz versions in NEC 0.25 micron
- Fujitsu TurboSPARC, 1996
- SPARC version 9
- a large committee with over 100 meetings
- major contributors -
Dave Ditzel (chairman),
Joel Boney (vice chairman, and chairman at the end),
Dave Weaver, Winfried Wilcke, Robert Yung, Bill Joy, Steve Chessin,
Steve Krueger, and Steve Kleiman
-
Dave Ditzel, SPARC Version 9 video, Sept. 1992
- "In 1991 [Bill Joy] did the basic pipeline design of
UltraSparc-I and its multimedia processing features....
More recently, Bill has led design investigations of
architectures for UltraSparc V...." (from executive bios at Sun)
- implementations
- Sun UltraSPARC I, 1995 - Les Kohn, Marc Tremblay,
Guillermo Maturana, and Robert Yung
- UltraSPARC II, 1997 - Les Kohn, Marc Tremblay
- UltraSPARC IIi - Kevin Normoyle
- UltraSPARC III, 2000 - Gary Lauterbach
- UltraSPARC IIIi - Kevin Normoyle
- UltraSPARC-IIIi+ - Samsong Wong
- UltraSPARC IV - started by Bill Lynch, then Joe Chamdani,
then Quinn Jacobson with the help of Gary Lauterbach
- UltraSPARC IV+ - major redesign done by Quinn Jacobson and
finished by Dale Greenley
- UltraSPARC V (cancelled) - Dan Leibholz, Wayne Yamamoto,
and Rick Hetherington
- UltraSPARC T1 (Niagara) - initially done by Les Kohn and
Kunle Olukotun, with help of William Bryg and Poonacha
Kongetira; after the Afara acquisition, the chief architect
role was moved to Rick Hetherington
- Niagara2 and 3 - Rick Hetherington
- Rock - chief architects Marc Tremblay and Shailender Chaudhry
- HaL SPARC64, 1995 -
Hisashige Ando (design manager), Winfried Wilcke, and Mike Shebanow
- HaL SPARC64 V (abandoned) - Mike Shebanow and ...
- Fujitsu SPARC64GP, 1999 (further development of Hal SPARC64) -
Takato Noda, Takumi Maruyama
- Fujitsu SPARC64 V, 2003 (new design based on GS8800B) -
Aiichiro Inoue, Takeo Asakawa
- Fujitsu SPARC64 V+, 2004 - Aiichiro Inoue, Yuji Yoshida
- Fujitsu SPARC64 VI, 2007 (2 cores on a chip) -
Aiichiro Inoue, Takumi Maruyama, Takeo Asakawa
- VIS, 1995 - Les Kohn, G. Maturana, Marc Tremblay, A. Prabhu,
and G. Zyner, with early contributions by
Tim van Hook, Robert Yung, and Bill Joy
Three Rivers
- PERQ - Brian Rosen, etc.
- microprogrammable, came with P-code variant interpreter
- PERQ-1, 1980
- PERQ T-1, 1981
- PERQ T-2, 1982
Weitek
- XL processor - Craig Hansen
- 1064/65/66/67 (FP data paths) - Craig Hansen
- used for both the original SPARC and MIPS R2000 implementations
Xerox
- Alto, 1973 - Chuck Thacker (primary designer),
also Ed McCreight, Butler Lampson, Bob Sproull, and Dave Boggs
- D*-series - Butler Lampson, Chuck Thacker, and Ron Rider
- Mesa byte-coded instruction set was designed by Butler Lampson
and Chuck Thacker
- D0, 1978 - Dolphin was TTL version
- D1, 1979 - Dorado was ECL version
- Dicentra - diskless router
- Daybreak (6085)
- Daisy - VLSI version, never manufactured
- B Lampson and K. Pier, "A Processor for a High-Performance Personal
Computer," ISCA, 1980
- K. Pier, "A Retrospective on the Dorado, a High-Performance Personal
Computer," ISCA, 1983 [lists project personnel]
- Star (8010), 1981
- AMD 29K bitslice implementation was called "Dandelion",
based on Butler Lampson "Wildflower" design, and ran a Mesa
virtual machine
- Jeff Johnson, et al., "The Xerox 'Star': A Retrospective,"
IEEE Computer, September 1989
Zilog
- Z8000 -
Bernard Peuto (architect)
- Masatoshi Shima (logic designer); Hiroshi Yonezawa (MMU);
Ross Freeman (peripherals); also contributions by Judy Estrin
- B. Peuto, "Architecture of a New Microprocessor," IEEE Computer,
Feb. 1979, pp. 10-21.
- M. Shima, "Demystifying Microprocessor Design,"
IEEE Spectrum, July 1979, pp. 22-30.
- Z80,000 - John Banning and Don Alpert
- D. Alpert, "Powerful 32-Bit Micro Includes Memory Management,"
Computer Design, October 1983, pp. 213-220.
need intro...
Apollo (see Apollo entry in
workstation processor section)
Masscomp (later Concurrent)
- first real-time UNIX box dual 68K's to deal with the page fault issue
- MC500/DP first multiprocessor UNIX box (asymmetric)
- Series 700 first SMP UNIX box
Tektronix
- Magnolia, 1979 - Clem Cole and Roger Bates
- first multi-68K based graphics workstation but problems in moving
to product
- later sold as a Smalltalk workstation
Three Rivers (see Three Rivers PERQ entry in
workstation processor section)
Xerox (see Xerox entry in
workstation processor section)
... more to do!
Chromatic Research
- MPact 1, 1995 - Steve Purcell
- MPact 2, 1997 -
- doubles the clock speed from 62 to 125 MHz, adds a
32-bit floating-point unit, 35-stage 3-D pipeline, and 2 KB
of texture cache
- Toshiba will use MPact 2 core in embedded DRAM with low power
- Chromatic was acquired by ATI in 1998
Equator / Hitachi
- MAP 1000 (Media Accelerated Processor), 1998
- company founded by John O'Donnell (Multiflow), Ben Cutler (Multiflow),
and Yatin Mundkur (SUN/Ross)
- compilers - Doug Gilmore (Multiflow), Tom Karzes (Multiflow and
MicroUnity), Jason Eckhardt (Convex), Evan Cheng, and Mei Ye
- several variants
- MAP 1000A / 1000TM
- MAP 3D, 1999 - for 3D graphics pipeline
- MAP CA, 2000 - for consumer applications (e.g., HDTV)
- MAP BSP, 2001 - for broadband signal processing
- acquired by Pixelworks in 2005
MicroUnity
- MicroUnity MediaProcessor - Craig Hansen
Philips
Because of the large market for x86-compatible processors, this is a special
section devoted to processor within that market.
See Christain Ludloff's sandpile.org
for detailed information on particular chips.
AMD (Advanced Micro Devices)
- AMD K5, 1996 - Mike Johnson, David Witt, and Dave Christie
-
AMD/NexGen K6, 1997 - Greg Favor
- AMD started internal K6 work as an extension of the K5 base, but
this was discarded in favor of buying NexGen and using their
Nx686 design relabelled as K6
- see
The Anatomy of a High-Performance Microprocessor (K6-2 3D-Now!
case study)
- AMD K6-2, 1998
- AMD K6-III, 1999
-
AMD Athlon (K7), 1999 - Dirk Meyer (Dir. Engr.), Fred Weber, ...
- x86-64 architecture - Kevin McGrath, Dave Christie, and Mike Clark
- AMD Opteron (K8), 2003 - Jim Keller and then Fred Weber
- Jim Keller left and the initial K8 design was canceled
- Fred Weber led the project to revise the K7 into a 64-bit core
- AMD "Bulldozer" family, 2011 - Chuck Moore, Mike Butler
- AMD "Zen" family, 2017 - Mike Clark, Jim Keller
Cyrix (see IDT/Centaur/VIA below)
- Cyrix 486 chips, 1992 - Mark Bluhm and Ty Garibay
- 5x86 (M1sc), 1995 - Mark Bluhm and Ty Garibay
- 5gx86 (MediaGX), 1997 - Forrest Norrod
- 6x86 (M1), 1996 - Mark Bluhm and Ty Garibay
- in-order, native x86 superscalar design
- dual pipelines
- register renaming
- 6x86MX / MII (M2), 1997 - Dan Green
- Cayenne core (ca. 1997) - dual issue of FXCH in FP/MMX unit
- MXi (graphics integrated with Cayenne core), 1997 - Doug Beard
- first VIA Cyrix III (Joshua, Jedi, Gobi)
- based on native x86 Cayenne core
- dropped in June 2000 in favor of Centaur WinChip/C5/Samuel
- MIII (M3, Jalapeno core, Mojave), 2000 - Ty Garibay and Mike Shebanow
started the design (1994-1997) and then Greg Grohoski took
over the project
- out-of-order, decoupled design (translate x86 to uops)
- cancelled in March, 2000
[Cyrix was formed in 1988 by a group of ex-TI folks. Initial products
were floating-point coprocessors.
National Semi bought Cyrix in Novermber 1997 for $550M.
National announced in May 1999 that it intended to sell Cyrix.
Via bought Cyrix in June 1999 (after renegotiating the price
from $300M to $167M) and then bought Centaur in August 1999 for $51M.
Cyrix was in Richardson, TX, and had approx. 330 staff size, while
Centaur was in Austin, TX, and had approx. 60 staff size. Supposedly
Cyrix had a burn rate of $10M/month at the time of the acquisition.
Most of the Cyrix folks left or were laid off after the acquisition.]
IDT / Centaur / VIA
- IDT-C6 (WinChip), 1997 - Terry Parks and Glenn Henry
- scalar issue, decoupled design (translate x86 into uops)
- 6 pipe stages
- WinChip 2 (C2, C6+), 1998
- WinChip 3 (C3) - sampled but never shipped
- WinChip 4 (C4) - design with 11 pipe stages reported in MPF
- Cyrix III (Samuel, C5, C5A), 2000 - Glenn Henry, ...
- 12 pipe stages
- C5B / Samuel II
- C5C / Ezra
- C5M / Ezra-T
- Matthew (integrated graphics)
- Via C3 / Nehemiah (C5X), 2003 - Glenn Henry, ...
- 16 pipe stages
- MMX units operate out-of-order
- Via Antaur - mobile
- Via C3 - desktop
- Via Eden - embedded
- CY (Esther)
- CZA
Intel
- Intel 8086 and 8088, 1978 - Stephen Morse and Bruce Ravenel
- S.P. Morse, B.W. Ravenel, S. Mazor, and W.B. Pohlman,
"Intel Microprocessors -- 8008 to 8086,"
IEEE Computer, October 1980, pp. 42-60.
From the acknowledgements section:
Many people played significant roles in the development of these
processors. Hence, it is not possible to single out a few for all the
credit. However, if forced to choose those people who played the most
significant roles on each chip, we can name the following: M.E. (Ted)
Hoff was the architect and Federico Faggin the chip designer of the
4004. Stanley Mazor contributed to the 4004 architecture as well as to
the architectures of the 8008 and 8080. Hoff and Hal Feeney were the
major contributors to the 8008 development. Faggin managed the
development of the 8080 and participated in defining its architecture,
with Masatoshi Shima doing the logic and circuit design. Roger Swanson
defined the new instructions for the 8085 while Peter Stoll and Andrew
Volk performed the 8085 logic and circuit design. The 8086 architecture
was defined by Stephen Morse and refined by Bruce Ravenel, with James
McKevitt and John Bayliss responsible for the logic and circuit design.
William Polhman managed both the 8085 and 8086 activities.
-
"Stephen Morse: Father of the 8086 Processor," Benj Edwards,
PC World, June 16, 2008
- 8087 (FPU) - John Palmer (chief), with significant contributions
by William Kahan, and implementation led by Bruce Ravenel
- 80186 - (Jim McKevitt?)
- 80286, 1982 - Bob Childs
- 80287 (FPU) - derived from 8087
- Intel IA32 - John Crawford and Patrick Gelsinger
-
MMX extensions - Uri Weiser (chief), Alex Peleg (lead), Bob Dryer,
Larry Mennemeier, David Bistry, and Millind Mittal
- SSE extensions -
- SSE2 extensions -
- implementations
- 80386, 1985 - John Crawford (chief), Jim Slager
- 80387 (FPU) - derived from 80287
- 80486, 1989 - John Crawford (chief)
- Pentium (P5), 1993
- Architecture/performance team: Don Alpert (chief), Jack Mills,
and Bob Dreyer
- The initial superscalar definition and feasibility study for
the Pentium integer pipeline was done by Uri Weiser, Yaakov Yaari,
and David Perlmutter at Intel's Haifa Design Center in late 1988 /
early 1989.
- Don Alpert and his team in Santa Clara extended this superscalar
framework in spring 1989.
- FPU: complete redesign of all algorithms and microarchitecture
by Harsh Sharangpani with contributions by William Kahan and
Peter Tang
- microarchitecture:
Ed Grochowski (integer), Ken Shoemaker (integer),
Harsh Sharangpani (floating point), and
Gary Hammond (protected mode)
-
John Crawford, Don Alpert, and Beatrice Fu, Pentium overview video,
June 1993
-
Daniel Deleganes, Pentium 90/100 video (Hot Chips VI),
August 1994
- Patrick Gelsinger, Desmond Kirkpatrick, Avinoam Kolodny,
and Gadi Singer,
"Coping with the Complexity of Microprocessor Design at Intel
– A CAD History"
[covers 1971 to 1993; also appears as
"Such a CAD!," IEEE Solid-State Circuits Magazine, Summer 2010,
pp. 32-43.]
- Pentium Pro (P6), 1995 - Bob Colwell (chief), Glenn Hinton (senior),
Dave Papworth (senior), Michael Fetterman, and Andy Glew
- Pentium w/MMX (P55), 1996 - also includes PPro branch prediction
- Pentium II, 1997 - P6 core
- Pentium III, 1999 - P6 core, adds SSE
- Pentium 4, 2001 -
Glenn Hinton (chief), Darrell Boggs, Douglas Carmean,
Patrice Roussel (lead on floating point),
Dave Sager, and Michael Upton
- new core, also adds SSE2
- initial design leadership by Bob Colwell, Glenn Hinton,
and Dave Papworth
- 30+ pipeline stages (20 disclosed in "branch misprediction pipeline")
- trace cache, 2-way multithreaded
- Pentium M, 2003 - Simcha Gochman
- low-power revision of P6 core, adds SSE2, fused uops
- Core microarchitecture (NGMA), 2006 - (Ofri Wechsler mgr.?)
- Atom microarchitecture, 2008 - Belli Kuttanna
P7, 1991-1994 (RISC-like 64-bit architecture definition effort;
led to Itanium)
- Don Alpert (chief architect)
- Gary Hammond (protected mode)
- Hans Mulder (integer)
- Harsh Sharangpani (floating point and lead microarchitect)
- Ken Shoemaker (x86 compatibility)
IA64 / Itanium
(see independence arch. processor section)
NexGen
- Nx586 (F86), 1995 - Mack McFarland was the first architect,
then Dave Stiles and Greg Favor worked on the design, and later
Korbin Van Dyke oversaw the implementation
- NexGen was a startup funded by Compaq, ASCII, and Kleiner Perkins
(founder was Thampy Thomas);
Nick Tredennick hired and managed the original
engineering team; people who followed Nick included Atiq Raza and
Dave Epstein (who led the chip into full production, 1990-1995)
- the F86 was described at 1989 Compcon and later renamed Nx586,
it required a FP coprocessor
- NexGen was bought by AMD in 1995
- NexGen Nx686 (see AMD K6 above in this section)
- Keith Diefendorff was hired as director of technical strategy
at NexGen in 1995 and worked on Nx686 at NexGen and then at
AMD until 1996
Rise
Transmeta
- Crusoe, 2000
- Efficeon, 2003
- internal 8-way VLIW, masked by code morphing software
need intro... MIT CONS machine, then CADR ...
Richard Greenblatt: The LISP Machine. November 1974
Tom Knight: CONS. November 1974
F. Knight, Jr., David A. Moon, Jack Holloway and Guy L. Steele, Jr.:
CADR, May 1979
Symbolics
- LM-2, 1980 - repackaged MIT CADR
- L-machine (3600), 1982 - Tom Knight, Bruce Edwards, Chris Terman
- G-machine, 1984 - 3600 architecture in gate arrays
- I-machine (Ivory), 1987 - single-chip processor, also used as a
coprocessor by others
LISP Machines, Inc. (LMI)
- LMI-CADR, 1980 - same as the MIT CADR
- LMI-LAMBDA, 1983 - CADR combined with a 68010
- K-machine, 1986 - Bruce Deffenbaugh, Joe Marshall, Robert Powell,
and Simon Willison
- new design, not descended from CADR
- hardware implementation by Robert Powell, Bruce Deffenbaugh,
and Kent Hoult
Texas Instruments
- Explorer, 1983 - Keith Diefendorff
- Explorer-II, 1987 - Keith Diefendorff
Xerox
need intro...
Patriot Scientific Corp.
- PSC1000, 1997 -
- 100 MHz, $10 in high volumes
Rockwell
- JEM1 - ? (Nick Mykris, mgr. of adv. uproc. section)
- 50 MHz, 60 mW, based on AAMP rather than picoJava core
Sun JavaChips
need intro...
Rational
- R1000, 1984 - Mike Devlin and Dave Stevenson
- Rational was founded by Paul Levy and Mike Devlin in 1981; Dave
Bernstein joined to lead the development team a year later
- R1000 was a microcoded design to support Ada, see US 4,791,550
- four models of the R1000 were designed (series 100, 200, 300, and
400; series 400 schematics and other documents have been placed
online by the Danish Data Historical Society)
- Rational sold about 300 machines in total; a decision was made in
1990 to leave the hardware business and concentrate on software
products
- Grady Booch
described the machine:
The R1000 was a horizontally microprogrammed machine with a 67 bit
single level virtual address space. This machine was in essence a
dual stack-based processor, with computation done on one path and
type checking on another. The R1000 was effectively a DIANA machine
(DIANA being the Descriptive Intermediate Attributed Notation for
Ada, a formal intermediate representation for the language). We
didn't store source code: source code was simply a pretty-printing
of the DIANA tree. Using DIANA with hardware acceleration made it
possible to do incremental compilation (unheard of at the time, for
strongly typed languages), easy refactoring (though that word had
not yet been invented), and incredibly fast integration (essential
for the large systems that we being built with Ada).
The credit for collecting information in this section goes to Phil Koopman.
He has found lots of designs but most with relatively low sales volume.
Phil has a web page that points to current sales sources of
stack processors.
Echelon
- Neuron, 1990 - Bruce Eisenhard
- 8-bit, 3-way multithreaded communication microcontroller
- sold as
Motorola MC1431x0 and as Toshiba TMPN31x0
Harris
- RTX 2000 (based on Novix NC6000 design), 1987 -
John Rible and Chris Malinowski
- John Rible added on to the design of Novix NC4016 to create the NC6000
for Novix. Novix then licensed the design to Harris Semiconductor.
- Chris Malinowski of Harris changed the NC6000 into a family of
microcontrollers: RTX 2000, RTX 2001, RTX 2010.
-
Phil Koopman's description of the RTX 2000
Novix
- NC4016, 1985 -
Chuck Moore (architect) with help from Bob Murphy and Greg Bailey
- NC6000, 1987 - John Rible (see Harris RTX 2000 above)
more to do...
(Phil Koopman describes this market in his
1996 ICCD paper.)
AMD (Advanced Micro Devices)
- 29000-derived
(see workstation processor section)
- 29030 - 2-bus, 8k icache, no dcache, interrupt controller, timer, jtag
- 29035 - 2-bus, 4K icache, no dcache, interrupt controller, timer, jtag
- 29040 - 2-bus, 8K icache, 4k dcache, interrupt controller, timer,
jtag, hardware multiply
- 29200 - 29000 core with parallel and serial ports, DMA, interrupt
controller, DRAM,
memory decode, and interface to laser printer engines
- 29205 - slightly reduced function version of 29200
- 29240 - like a 29200, with 4K icache, 2K dcache, hardware multiply,
16 entry MMU
- 29245 - like a 29200, with 4K icache, 16 entry MMU
- 29243 - like a 29240, 32 entry MMU, DRAM parity, no printer engine I/F
- x86-derived
ARM (Advanced RISC Machines, Ltd.)
- ARM - Sophie Wilson
(Also involved: Dave Jaggar wrote the ARMv4 Architecture book, David Seal
oversaw the arithmetic, and Edward Nevill selected the Thumb opcodes after
the basic idea was conceived by Dave Jaggar.)
- ARM1, 1985 - Steve Furber (who now works at Manchester University on
asynchronous ARMs called Amulet)
- ARM2, 1986 - Steve Furber
- ARM3, 1989 - Alasdair Thomas
- [There was no ARM4 or ARM5. Apple's Larry Tesler suggested a direct
move to ARM6 for marketing reasons (the 486 and 68040 had been around
for some time) and a consistent naming scheme - ARM6 for the core,
ARM60 for a CPU chip (e.g. in the 3DO machine), ARM610 for an enhanced
CPU with a cache (e.g. in the Newton or Acorn RiscPC). This scheme
was later extended so that 4 digits is a deeply embedded processor
with peripherals - most of these are based on ARM7 (ARM7500, ARM7500FE,
ARM7110) with a couple of StrongARM1 based ones (SA1100, SA1500).
Under this naming scheme, ARM1 would have been ARM10, ARM2 would have
been ARM20, ARM3 would have been ARM200 (ARM2 plus cache) and ARM250
would have been ARM2500.]
- ARM 6(10), 1993 - Alasdair Thomas
- ARM 7(10), 1994 - Dave Jaggar (7 core) and Simon Watt (710 cpu)
- ARM7TDMI - Dave Jaggar (architect) and Keith Clarke (implementation)
- ARM7500FE - Peter Harrod
- ARM 8(10), 1995 - Guy Larri and Neil Robinson
- ARM9(10,40) - Ian Devereux, Guy Larri
- ARM10 - Dave Jaggar, Gerard Williams, Chris Hinds
(floating-point), Raney Southerland (implementation)
- ARMFPA10 - Pete Harrod
- ARMFPA11 - Peter Harrod and David Seal
- ARMVFP10 - Chris Hinds, Dave Jaggar, Eric Schorn (implementation)
- ARM11 - Richard Grisenthwaite, Ian Deveraux, Chris Hinds
(floating-point)
- Cortex A8 - Gerard Williams, Raney Southerland (implementation),
Chris Hinds (floating-point)
- (see also DEC StrongARM)
DEC
- StrongARM
-
StrongARM 110, 1996
- Rich Witek (lead), Greg Hoepnner, Ray Stephany, Jim Montanaro, +
-
StrongARM 1100, 1997 - Rich Witek (lead microarchitect),
Ray Stephany (implementation)
- as part of a lawsuit settlement between DEC and Intel,
Intel acquired StrongARM and the DEC design team left
-
Intel StrongArm page
- (see also Intel XScale)
Hitachi
- SuperH RISC -
- SH-1/SH-2, 1993 -
- SH-3, 1994 -
- SH-4, 1997 -
Intel
- Intel 8051 - ? (8-bit?, check on this)
- Intel x86 derived
- Intel i960 - Glen Myers
- original implementation -
- ...
- i960 CA (superscalar), 1989 - Glenn Hinton and Frank Smith
- i960 MM -
- ...
- SA,SB,KA,KB,JA,CF
- HD,HT - Jay Heeb and Tim Jehl microarchitecture
- R series has I2O
- ...
- i960 JX -
- ...
-
i960 CA/MM/JX comparison
-
XScale
- XScale core and 80200 processor - Tom Adelmeyer (architecture),
Steve Strazdus and Paul Meyer (microarchitecture)
MIPS
- MIPS-II-derived (32-bit,
see workstation processor section)
- MIPS-16 (32-bit data/16-bit compressed instructions), 1996 -
Earl Killian and Hartvig Ekner
Motorola / Freescale
- 68000-derived
- Coldfire - Joe Circello
- Motorola Unfolds ColdFire Roadmap, Microprocessor Report,
September 16, 1996 [check if on-line]
- ColdFire: A Hot Architecture, Byte, May 1995 [get link to on-line copy]
- 5102, 1995 -
- 520x? -
- m-core - Brian Lucas, Kent Moat, Mike Schuette, Ray Essick, Bill Moyer,
and Hunter Scales.
- PowerPC-derived
- 400 series ...
- 500 series ...
- 602?
- 800 series ...
National Semiconductor
- Embedded versions of National Semiconductor 32K
- NS32CG16 (Guppy) - based on the original 32016 without MMU support
but with added software and hardware bitblt support, used in the
Canon LBP printer
- NS32CG160 (Shark) - uses same core as Guppy (CG) and adds timers,
DMAC, and ICU; designed for LBP
- NS32FX16 (Goldfish, a.k.a. Wanda) - used the CG core and added
a DSP accelerator designed specifically for fax applications
where the integer machine will do the printing and the DSP part
will do a soft modem
- NS32FX164/161 and 32FV16 (with various on-chip RAM and
Sigma-Delta codec configurations, Goldfish-II) - used the same
core as Goldfish but with a more aggressive DSP accelerator,
biggest success was as the sole processing unit within the
HP OfficeJet (responsible for everything starting with the
modem and ending with rendering and printing)
- NS32AM160/161/162/163 - all with the same processing units as
the Goldfish-II and added circuitry required to implement a
Digital Answering Machine, first or one of the first full
system-on-a-chip solutions, with biggest success being the
whole family of AT&T digital answering machines
- NS32GX320 (Barracuda) - used the 32532 core minus the on-chip MMU,
used in multifunction peripherals
-
CompactRISC - CR16A and CR32A done by Gideon Intrater, and
CR16B done by Alon Naveh
- CompactRISC is a load/store architecture with a fixed-length
instruction format that implements a very small subset of the
original NS32K instruction set. Traps are treated similarly;
but the register file is significantly larger. Additionally,
there are some new DSP instructions and a new calling convention.
- See also D. Alpert, A. Averbuch, and O. Danieli, "Performance
comparison of load/store and symmetric instruction set architectures,"
ISCA-17, Seattle, 1990, pp. 172-181.
- Implementations
- NS32SF641 - essentially the
Swordfish design changed to implement the CompactRISC inst. set
- Gideon Intrater took over responsibility for the design after
Don Alpert left for Intel
- Piranha, 1995 - Gideon Intrater
- HPC (embedded 16-bit) - Ralph Haines
- Intel x86 derived
- NS486 embedded controller - Mario Nemirovsky & others
Rockwell
Transputer
- Transputer - Iann Barron (main), David May, Roger Shepherd, and
Peter Thompson
- Iann Barron was the main architect and was responsible for
putting the team together and providing the concepts.
- David May provided the principal details of the transputer
instruction set, its communications, and the occam language.
- Roger Shepherd, under David May's guidance, provided the
details of the timer.
- Peter Thompson developed the communications architecture of
IEEE 1355, with its simple but flexible virtual
channels and hardware routing technology.
- "All the ideas were bounced off other people, many of whom
contributed by asking awkward questions, finding holes in what
was proposed, simply writing down what was proposed, trying to
implement it and finding awkwardnesses that needed to be cleaned
up, and even asking customers what they wanted. But none of
these people would have come together without Iann Barron."
- implementations
- various test chips
- T2 -
- T4 - Guy Harriman
- T8 - Mark Homewood
- T9 - Brian Parsons
- T9000 (1988-1993)
- Overall Manager: Clive Dyson
- Chief architect: Roger Shepherd (with help from Dave May)
- Communications: Pete Thompson/Rob Simpson
- DSLink (IEEE 1355 and also in 1394 [firewire]): Robert Simpson
- CPU pipelining: Brian Parsons
- Implementation team leaders:
- CPU: Peter Barnes (microcode), Dave Greenhill (datapath)
- Cache/memory crossbar: Richard Gammack
- External memory interface: Mike Boland
- FPU: Simon Knowles
- Communications: Rob Simpson
-
May, Shepherd, and Thompson, "The T9000 Transputer," ICCD 1992
- ST20 embedded processor (SOC) (1992-1995)
- originally known as RMC (re-usable micro core)
- Overall manager: Bob Krysiak
- Architect: Rob Simpson
- Implementors:
- Andy Harley (microcode)
- Steve Felix (ALU)
- Graham Matthew (Memory system and system interconnect)
- ST20-C1 - Dave Shepherd and Julian Lewis
-
Transputer archive
-
Geoff Barrett, "Formal methods applied to a floating point number
system" [for T800]
to be done - DSP architectures include
special instructions for processing digital signal data
The following early history of DSP chips given by
Murat Kunt, Swiss Federal Inst. of Tech., at the
1990 CERN School of Computing
1978 AMI S2811
1979 Intel 2920/21 (telecomm)
1979 Bell Labs DSP 1 (internal)
1980 NEC uPD7720
1980 Analog Devices ADSP-2100
1981 IBM Hermes (internal)
1982 Hitachi 61810
1982 Texas Instruments 32010
representative chips
GP DSPs: AT&T DSP16, DSP32; Motorola DSP56116, DSP5600x, DSP 9600x;
TI TMS320Cxx; Analog Devices 2100
Digital filter specific DSPs: INMOS A100, LSI64240, Motorola DSP56200, Zoran
FFT specific DSPs: TRW2310, HDSP66110, UT69532, Zoran
Texas Instruments
- TMS320 series
- The speech synthesis chip developed by George L. Brantingham and
Richard H. Wiggins in 1978 (U.S. Patent No. 4,209,844 granted in 1980)
was the beginning of TI's DSP efforts. It used an on-chip 8-bit
digital-to-analog converter to transform digital information processed
through the filter into synthetic speech. It used a multistage
multiplier and accumulator architecture.
- TMS320C3x - first 32-bit single-chip floating-point DSP
- TMS320C4x - first multiprocessing DSP easily interconnectable in
various configurations of meshes, grids, rings, etc.
- TMS320C6x - first single-chip 8-wide-VLIW DSP
(see VLIW processor section)
... more to do
Nintendo 64
- main processor is a MIPS R4300 (slightly modified)
- Reality Co Processor (RCP) - team effort
- Mary Jo Doherty was the lead designer for the (RSP)
signal processor portion of the chip
- Phil Gossett was the lead designer for the (RDP)
graphics portion of the chip
- Tim van Hook brought many ideas to the RCP
from his earlier work with the "MIPS Multi Media Engine"
Sony Playstation 2
My thanks to the following for their help in identifying some of
the folks listed above and telling me about the projects in which
they were involved:
John Ahlstrom, Don Alpert, Carl Alsing, Mitch Alsup, Steve Anderson,
Tom Anderson, Siamak Arya, Pete Bannon, Allen Baum, Rich Belgard,
Dave Bernstein, Mark Bluhm, Joel Boney, David Boreham,
David Boundy, Henry Burkhardt III, Brian Case, Dave Christie, Clem Cole,
Bob Colwell, Chuck Corley, Charlie Crabb, Jim Dehnert, Marvin Denman,
Keith Diefendorff, Jason Eckhardt, John Edmondson, Dave Epstein,
Eric Fischer, Russell Fish, Alan Folmsbee, David Fotland,
Philip Freidin, Robert Garner, Doug Gilmore, Ivan Godard,
George Gray, Dan Green, Greg Grohoski, Mike Haertel, Andrew Haley,
Chris Hinds, Peter Hoffman, Jan Hoogerbrugge, Marty Hopkins, Hugh Hyatt,
Gideon Intrater, Dave Jaggar, Earl Killian, Phil Koopman,
Al Kossow, Ashok Kumar, Steven Kunkel, Dan Lau, Guy Lemieux,
Jud Leonard, Tim Leonard, Richard Lethin, Bill Mangione-Smith,
John Mashey, Shawn McLean, Avraham Menachem, Steve Morse,
Claude Moughanni, Steve Muchnick,
Harm Munk, Michael O'Connor, Vojin Oklobdzija, Tim Olson,
Ken Omohundro, Howard Owens, Yale Patt, Dave Patterson,
Jeff Rupley, John Ruttenberg, Ulf Samuelsson, Harsh Sharangpani,
Ray Simar, Robert Simpson, Peter Song, Zalman Stern, H.W. Stockman,
Steve Strazdus, Bob Supnik, Sergey Svishchev, Ran Talmudi,
Julian Thomas, Ross Towle, Nick Tredennick, Marc Tremblay,
Stuart Tucker, Paul Walker, David Weinzierl, Uri Weiser,
Turner Whitted, Sophie Wilson, Steve Wilson, Bill Worley,
and Mike Ziegler.
(My apologies to these individuals for any misunderstandings on my part
about the information they have graciously shared with me; the errors in
the architects list above remain mine.)
Revision history
[History page]
[Mark's homepage]
[CPSC homepage]
[Clemson Univ. homepage]
mark@cs.clemson.edu