Interesting Computer Architecture Patents
(quite incomplete - I intend to add as I come across)
- Early dynamic scheduling efforts
- US 3,346,851 (1967) Thornton and Cray (CDC),
"Simultaneous multiprocessing computer system" - CDC 6600
- US H1291 (1994) Hinton and Smith (Intel) - i960CA
- Early static scheduling (VLIW) efforts
- US 3,771,141 (1973) Culler (Culler-Harrison),
"Data processor with parallel operations per instruction"
- US 4,295,193 (1981) Pomerene (IBM),
"Machine for multiple instruction execution"
- US 4,553,203 (1985) Rau, et al. (TRW)
"Easily schedulable horizontal computer"
- US 5,121,502 (1992) Rau, et al. (Cydrome/HP)
"System for selectively communicating instructions from memory
locations simultaneously or from the same memory locations
sequentially to plurality of processing [units]"
- Instruction sequencing
- US 3,234,523 (1966) Blixt, et al. (Sperry Rand),
"Phase controlled instruction word format"
- US 4,833,599 (1989) Colwell, et al. (Multiflow),
"Hierarchical priority branch handling for parallel execution in
a parallel processor"
- Instruction predecoding
- US 4,437,149 (1984) Pomerene, et al. (IBM),
"Cache memory architecture with decoding"
- US 5,442,760 (1995) Rustad, et al. (Dolphin),
"Decoded instruction cache architecture with each instruction
field in multiple-instruction cache line directly connected to
specific functional unit"
- Instruction folding/collapsing/optimization during predecoding
- US 5,101,341 (1992) Circello, et al. (Edgcore),
"Pipelined system for reducing instruction access time by
accumulating predecoded instruction bits [in] a FIFO"
- US 5,163,139 (1992) Haigh, et al. (Hitachi),
"Instruction preprocessor for conditionally combining short
memory instructions into virtual long instructions"
- US 5,377,339 (1994) Saito, et al. (Toshiba),
"Computer for simultaneously executing instructions temporarily
stored in a cache memory with a corresponding decision result"
- Instruction optimization during execution
- US 5,699,536 (1997) Hopkins and Nair (IBM),
"Computer processing system employing dynamic instruction formatting"
- Indirect VLIW
- US 5,299,321 (1994) Iizuka (Oki),
"Parallel processing device to operate with parallel execute
instructions"
- US 5,649,135 (1997) Pechanek, et al. (IBM),
"Parallel processing system and method using surrogate instructions"
- US 6,356,994 (2002) Barry and Pechanek (BOPS),
"Methods and apparatus for instruction addressing in indirect
VLIW processor"
US 2,636,672 (filed 1949, awarded 1953))
Hamilton, Seeber, Rowley, and Hughes,
Selective Sequence Electronic Calculator (IBM SSEC)
US 3,120,606 (filed June 26, 1947, awarded Feb. 4, 1964)
Eckert and Mauchly,
Electronic Numerical Integrator And Computer (ENIAC)
US 2,950,465 (filed 1954, awarded 1960)
Fox, Bartelt, Crawford, and Rochester,
Electronic Data Processing Machine (IBM 701)
[see also US 2,974,866; US 3,197,624; US 3,213,373]
US 3,200,379 (filed 1961, granted 1965)
King and Barton, Digital Computer
(Burroughs B5000)
US 3,400,371 (filed 1964, awarded 1968)
Amdahl, et al., Data Processing System
(IBM S/360)
US 3,315,235 (filed 1964, awarded 1967)
Carnevale, et al., Data Processing System
(IBM S/360 Model 30)
US 3,319,226 (filed 1962, granted 1967)
Mott, et al., Data Processor Module
(Burroughs D825, thanks to David Burns for id)
US 3,401,376 (filed 1965, granted 1968)
Barnes, et al., Central Processor
(Burroughs 8500, thanks to David Burns for id)
US 4,766,566 (filed 1986, awarded 1988)
Chuang, superscalar RISC (IBM Cheetah)
US 4,992,938 (filed 1990, awarded 1991)
Cocke, et al., register renaming (IBM America)
US 5,127,091 (filed 1989, awarded 1992)
Boufarah, et al., branch processing unit (IBM RS/6000)
more determination needed:
5,488,729 (1996) - SuperSPARC?
5,640,588 (1997) - SuperSPARC?
4,939,638 (1990) - Stellar GS1000 multithreading
other:
3,699,529 (1972) - token ring
[History page]
[Mark's homepage]
[CPSC homepage]
[Clemson Univ. homepage]
mark@cs.clemson.edu