Subword parallelism and graphics/multimedia support

Mark Smotherman
Last updated: September 2007

Summary: TBD

(under construction)

... intro to be written ...

The term SIMD was originally defined in 1960s as category of multiprocessor with one control unit and multiple processing elements - each instruction is executed by all processing elements on different data streams, e.g., Illiac IV. Today the term is used to describe partitionable ALUs in which multiple operands can fit in a fixed-width register and are acted upon in parallel.

(other terms include subword parallelism, microSIMD, short vector extensions, split-ALU, SLP / superword-level parallelism, and SIGD / single-instruction-group[ed]-data)

• actually Illiac IV also provided this and called it "dual arithmetic"

• earliest use may be in Lincoln Labs TX-2 in late 1950s:

        The structure of the arithmetic element can be altered under program
        control.  Each instruction specifies a particular form of machine in
        which to operate, ranging from a full 36-bit computer to four 9-bit
        computers with many variations.  Not only is such a scheme able to
        make more efficient use of the memory in storing data of various word
        lengths, but it also can be expected to result in greater over-all
        machine speed because of the increased parallelism of operation.
  
        Peak operating rates must then be referred to particular configurations.
        For addition and multiplication, these peak rates are given in the
        following table:
  
                   PEAK OPERATING SPEEDS OF TX-2
           Word Lengths      Additions    Multiplications
            (in bits)        per second     per second
                36             150,000        80,000
                18             300,000       240,000
                 9             600,000       600,000
        

• Univac 1107 (ca. 1962) - a 36-bit machine that included add/subtract halves instructions (two 18-bit operations in parallel) and add/subtract thirds instructions (three 12-bit operations in parallel)

• Intel i860 (ca. 1989) added three packed graphics data types (e.g., eight 1-byte pixel values per 64-bit word) and a special graphics function unit (e.g., z-buffer interpolation)

• Motorola 88110 (ca. 1991) included six graphics data types and performed saturating arithmetic

• Other ISA extensions
  • HP MAX (1994) - Media Acceleration Extensions (in PA 7100LC)
  • HP MAX-2 (1995)
  • SPARC VIS (1995) - Visual Instruction Set
  • Alpha MVI (1996) - Motion Video Instructions
  • Intel MMX (1996) - Multimedia Extension
  • MIPS MDMX (1996) - MIPS Digital Media Extensions
  • AMD 3DNow! (1998)
  • PowerPC AltiVec (1998)
  • Intel SSE (1999) - Streaming SIMD Extension
  • Intel SSE2 (2001)

• Multimedia processors
  • TI MVP
  • Microunity Mediaprocessor
  • Chromatic Mpact 1 and 2
  • Philips Trimedia

  • others
    • Analog Devices TigerSHARC
    • Equator MAP1000
    • Fujitsu MMA
    • Matsushita MCP
    • Mitsubishi D30V
    • Sharp DDMP
    • Sony PS-2 Emotion Engine
    • (more to do)

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  Acknowledgements

  My thanks to Don Alpert for his help.

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  mark@cs.clemson.edu