Flipper interrupt status bits:

/*
 * Status Register Bits
 * These are interupt status indicators.
 */
#define  FL_STAT_ERRINT    0x00000040
#define  FL_STAT_MARKINT   0x00000020
#define  FL_STAT_DLETINT   0x00000010
#define  FL_STAT_DLERINT   0x00000008
#define  FL_STAT_FEINT     0x00000004
#define  FL_STAT_FFREDINT  0x00000002
#define  FL_STAT_RFREDINT  0x00000001

FFred interrupt status bits: ffred->intr_status_reg;
/*
 * Interrupt Status/Mask register
 */
/* Pre-Atlantic */
#define F_CM_PARERR        0x8000   /* Control memory parity error         */
#define F_NORM_PM_PARERR   0x4000   /* Normal (non-CBR) packet mem error  */
#define F_CBR_PM_PARERR    0x2000   /* CBR packet memory error       */
#define F_TCQ_NOT_EMPTY    0x1000   /* TCQ went non-empty            */
#define F_TCQ_FULL         0x0800   /* TCQ full             */
#define F_TCC_FULL         0x0400   /* Cell counter overflowed       */
#define F_TRANSMIT_DONE    0x0200   /* Xmit done (if XD_INTT set in desc) */
#define F_CBR_DONE         0x0100   /* CBR done             */
#define F_RQ_A_MIS         0x0080   /* Rate queue in bank A missed service*/
#define F_RQ_B_MIS         0x0040   /* Rate queue in bank B missed service*/

FFred State Register: ffred->state_reg
/*
 * State Register
 */
/* Common */
#define F_OFF_LINE      0x8000   /* FFRED on line     */
#define F_PRQ_FULL      0x4000   /* PRQ full       */
#define F_PRQ_EMPTY     0x2000   /* PRQ empty         */
#define F_TCQ_EMPTY     0x1000   /* TCQ empty         */
#define F_CM_ERROR      0x0800   /* Control memory parity error   */

RFred interrupt status bits: rfred->intr_status_reg;

/*
 * Interrupt Status/Mask Register
 */
/* Pre-Atlantic */
#define R_CBR_CTR_OF    0x2000   /* Sync counter overflow   */
#define R_CM_PARERR     0x0400   /* Control memory parity error   */
#define R_LRG_FREEQ_MT  0x0200   /* No Large free descriptor   */
#define R_SML_FREEQ_MT  0x0100   /* No Small free descriptor   */
#define R_PCQ_FL_I      0x0040   /* Complete queue full     */
#define R_CBRQ_FL_I     0x0020   /* Sync fifo full    */
#define R_CBR_RCVD      0x0002   /* Sync cell received      */
#define R_PKT_CTR_OF    0x8000   /* Drop packet counter overflow  */
#define R_ERR_CTR_OF    0x4000   /* Error cell counter overflow   */
#define R_CELL_CTR_OF   0x1000   /* Received cell counter o-flow  */
#define R_FREEQ_MT      0x0200   /* No free descriptor      */
#define R_EXCPQ_FL_I    0x0080   /* Exception queue full    */
#define R_RAWQ_FL_I     0x0010   /* Flow control fifo full  */
#define R_EXCP_RCVD     0x0008   /* Excepton error occurred */
#define R_PKT_RCVD      0x0004   /* Packet received      */
#define R_RAW_RCVD      0x0001   /* Flow control cell received */

RFred State Register: rfred->state_reg
/*
 * State Register
 */
/* Pre-Atlantic */
#define R_CBRQ_FULL     0x0200   /* Sync fifo full    */
#define R_CBRQ_EMPTY    0x0100   /* Sync fifo empty      */
#define R_PCQ_FULL      0x0020   /* packet complete queue full */
#define R_PCQ_EMPTY     0x0010   /* packet complete queue empty   */
#define R_LRGQ_FULL     0x0008   /* Large descriptor queue full   */
#define R_LRGQ_EMPTY    0x0004   /* Large descriptor queue empty  */
#define R_SMLQ_FULL     0x0002   /* Small descriptor queue full   */
#define R_SMLQ_EMPTY    0x0001   /* Small descriptor queue empty  */
#define R_OFF_LINE      0x8000   /* Main state machine state   */
#define R_RAWQ_FULL     0x0800   /* Flow control fifo full  */
#define R_RAWQ_EMPTY    0x0400   /* Flow control fifo empty */
#define R_EXCPQ_FULL    0x0080   /* Exception queue full    */
#define R_EXCPQ_EMPTY   0x0040   /* Exception queue empty   */
#define R_PCQ_EMPTY     0x0010   /* Packet complete queue empty  */
#define R_Q_EMPTY       0x0004   /* Descriptor queue empty  */