Memory Organization:

Three separate memories are in play:
   - System memory (the main memory of the host)
   - Control ram (Adapter local control memory)
   - Buffer ram  (Adapter local buffer memory)

System memory contains

   - The tables of 256 descriptor list elements (DLEs)
   - Host buffers

DLE structure

   DLE's are used to control the DMA transfer of data between
   system RAM and Adapter local buffer RAM

   Structure is as follows:

   0x00 - 32 bit host physical memory address
   0x04 - 24 bit adapter local buffer address
   0x08 - 17 bit transfer byte count
   0x0c - Mode word (contains PRQ disable and INT enable)
   0x0e - New value for TPRQ write register

   DLE lists are managed at the driver level by four
   pointers contained in the softc structure.

   -  list->list_start
   -  list->list_end
   -  list->list_read
   -  list->list_write

Control ram contains
   - Segmentation descriptor table
   - The packet ready queue
   - The transmit complete queue

   Descriptor table structure
      0x0   Descriptor mode bits (includes CMPL_INTR and EOM_EN)
      0x2   VCI
      0x4   Reserved
      0x6   Length
      0x8   High part of address in local buffer RAM
      0xA   Low part of address in local buffer RAM
      0xC   Reserved...

   The packet ready queue

      A table of up to 8192 descriptor numbers.
      Each is an index into the buffer descriptor table
      The queue is managed by 4 FFRED registers

       *  start
       *  end
       *  read
       *  write

       Both are initialized to point to the start of the queue
       To initiate segmentation it would appear that filling
       a slot and incrementing the write pointer is the thing
       to do.

       It also appears that this can be done "automagically"
       via the DLE interface. This is done by setting the
       new value of the write pointer in the DLE.

       To initiate a transfer, one sets the number of DLE's
       to be processed in the transaction count register.


/*
 * Device offsets
 */
/* Pre-Atlantic */

#define  FFRED_OFFSET      0x00000     /* FFRED registers */
#define  RFRED_OFFSET      0x01000     /* RFRED registers */
#define  FECR_OFFSET       0x02000     /* Front end control register */
#define  SUNI_OFFSET       0x02800     /* SUNI registers */
#define  FLIP_OFFSET       0x03000     /* Flipper Internal registers */
#define  CONFIG_OFFSET     0x04000     /* Configuration registers */
#define  TX_TC_OFFSET      0x05000     /* Tx transaction counter */
#define  RX_TC_OFFSET      0x05004     /* Rx transaction counter */
#define  FFRED_MEM_OFFSET  0x10000     /* FFRED control RAM */
#define  RFRED_MEM_OFFSET  0x20000     /* RFRED control RAM */

FFred Control Memory Layout: (This Layout is for the Small memory model)

#define F_DESC_START            0      /* Descriptor table start        */
#define F_TCQ_START      ( 4*1024)     /* Transmit complete queue start */
#define F_PRQ_START      ( 5*1024)     /* Packet ready queue start      */
#define F_VC_START       (32*1024)     /* VC table start                */

RFred Control Memory Layout:

#define R_DESC_START               0       /* Descriptor table start  */
#define R_LFQ_START         ( 8*1024)      /* Large buffer free queue start*/
#define R_SFQ_START         ( 9*1024)      /* Small buffer free queue start*/
#define R_PCQ_START         (10*1024)      /* Packet complete queue start   */
#define R_EXCP_START        (11*1024)      /* Exception queue start   */
#define R_REASSM_START      (16*1024)      /* Reassembly table start  */
#define R_VC_START          (32*1024)      /* VC table start    */


/*
 * Flipper control registers
 */

typedef struct _fl_internal
{
   uint_t   fl_ctrl;          /* general purpose flipper control */
   uint_t   fl_status;        /* interrupt status */
   uint_t   fl_mac1;          /* lower 32 bits of mac */
   uint_t   fl_mac2;          /* ID etc & upper 16 bits of mac */
   uint_t   fl_ext_reset;
   uint_t   fl_int_reset;
   uint_t   fl_fpcnt;
   uint_t   fl_pci_page;      /* used for 64 bit addressing */
   uint_t   fl_transmit_list; /* Pre-Atlantic only */
   uint_t   fl_receive_list;  /* Pre-Atlantic only */
   uint_t   fl_eeprom_access;
   uint_t   fl_queue_size;
   uint_t   fl_mark_state;
/*
 * the cell_read_ptr, write_ptr, cells_avail, last_addr registers
 * assume bits 1:0 are 0
 */
   uint_t   fl_cell_read_ptr;
   uint_t   fl_cell_write_ptr;
   uint_t   fl_cells_avail;
   uint_t   fl_last_addr;
} fl_internal_t;