/* * Copyright (C) 1993 * Interphase Corporation, Dallas, TX 75234 * All Rights Reserved * * This code contains confidential information and trade secrets of * Interphase Corporation which shall not be reproduced or transferred * to other programs or disclosed to others or used for manufacturing * or any other purpose without prior written permission of Interphase * Corporation. Use of copyright notice is precautionary and does not * imply publication or intent thereof. */ /*H * FILE: ia_conf.h * * DESCRIPTION: * This files contains driver tunable parameters such as number * of board transmit buffers, size of Transmit Complete Queue, etc. * * FUNCTIONS: * EXPORTED: * * STATIC: * * GLOBAL DATA: * */ #ifndef _IA_CONF_H #define _IA_CONF_H /* * Tx and Rx buffer sizes. Same for the controller and the host */ #define TX_BUF_SIZE ( 2*1024) /* Tx buffer size */ #define RX_BUF_SIZE ( 2*1024) /* Rx buffer size */ #define RX_BUF_SIZE_ICHIP (RX_BUF_SIZE - 64) /* size used by the ichip */ /* * Number of controller buffers and DLEs */ #define NUM_TX_DESC_128 16 /* Number of Tx buffers */ #define NUM_RX_DESC_128 32 /* Number of Rx buffers */ #define NUM_TX_DESC_512 16 /* Number of Tx buffers */ #define NUM_RX_DESC_512 30 /* Number of Rx buffers */ #define NUM_TX_DESC 16 /* Number of Tx buffers */ #define NUM_RX_DESC 60 /* Number of Rx buffers */ #define MAX_SGE 2 /* Max scatter/gather elements */ #define TX_DELAY 500 #define TX_RETRIES 40 /* * Number of host buffers */ #define NUM_TX_BUFS_128 NUM_TX_DESC_128 /* Number of transmit buffers */ #define NUM_TX_BUFS_512 NUM_TX_DESC_512 /* Number of transmit buffers */ #define NUM_TX_BUFS NUM_TX_DESC_128 /* Number of transmit buffers */ #define NUM_RX_BUFS NUM_RX_DESC_128 /* Number of receive buffers */ #define NUM_RX_BUFS_MIN 5 /* Minimum #of receive buffers*/ #define RX_SMALL_PACKET 2048 #define RX_VERY_SMALL_PACKET 128 /* * Controller packet memory layout. * Numbers are offset from the start (or the end) */ #define RAM_SIZE_128 (128 * 1024) /* Total RAM size */ #define RAM_SIZE_512 (512 * 1024) /* Total RAM size */ #define RAM_SIZE (1024 * 1024) /* Total RAM size */ #define TX_PACKET_RAM 0 /* Transmit packet memory */ #define TX_RAW_RAM (4 * 1024) /* Transmit raw cell memory */ #define TX_CBR_RAM (3 * 1024) /* Transmit CBR cell memory */ #define RX_RAW_RAM (2 * 1024) /* Receive raw cell memory */ #define RX_CBR_RAM (1 * 1024) /* Receive CBR cell memory */ /* * F-FRED control memory layout. * Numbers are offset from the start of this memory */ /* Common */ #define F_DESC_START 0 /* Descriptor table start */ #define F_TCQ_START ( 4*1024) /* Transmit complete queue start */ #define F_PRQ_START ( 5*1024) /* Packet ready queue start */ #define F_VC_START (32*1024) /* VC table start */ #define F_TCQ_START_128K ( 4*1024) /* Transmit complete queue start */ #define F_PRQ_START_128K ( 5*1024) /* Packet ready queue start */ #define F_VC_START_128K (32*1024) /* VC table start */ #define F_TCQ_START_512K (16*1024) /* Transmit complete queue start */ #define F_PRQ_START_512K (20*1024) /* Packet ready queue start */ #define F_VC_START_512K (128*1024) /* VC table start */ #define F_TCQ_START_1M (32*1024) /* Transmit complete queue start */ #define F_PRQ_START_1M (40*1024) /* Packet ready queue start */ #define F_VC_START_1M (256*1024) /* VC table start */ /* Atlantic only */ #define F_CBR_TBL_START ( 6*1024) /* CBR table start */ #define F_VBR_TBL_START ( 8*1024) /* VBR table start */ #define F_ABR_TBL_START (10*1024) /* ABR table start */ #define F_ABR_TBL_START_128K (10*1024) /* ABR table start */ #define F_ABR_TBL_START_512K (40*1024) /* ABR table start */ #define F_ABR_TBL_START_1M (80*1024) /* ABR table start */ #define F_UBR_TBL_START (12*1024) /* UBR table start */ #define F_UBR_TBL_START_128K (12*1024) /* UBR table start */ #define F_UBR_TBL_START_512K (48*1024) /* UBR table start */ #define F_UBR_TBL_START_1M (96*1024) /* UBR table start */ #define F_VBR_WQ_START (16*1024) /* VBR Work Queue */ #define F_VBR_WQ_START_128K (16*1024) /* VBR Work Queue */ #define F_VBR_WQ_START_512K (64*1024) /* VBR Work Queue */ #define F_VBR_WQ_START_1M (128*1024) /* VBR Work Queue */ #define F_ABR_WQ_START (18*1024) /* ABR Work Queue */ #define F_ABR_WQ_START_128K (18*1024) /* ABR Work Queue */ #define F_ABR_WQ_START_512K (72*1024) /* ABR Work Queue */ #define F_ABR_WQ_START_1M (144*1024) /* ABR Work Queue */ #define F_UBR_WQ_START (20*1024) /* UBR Work Queue */ #define F_UBR_WQ_START_128K (20*1024) /* UBR Work Queue */ #define F_UBR_WQ_START_512K (80*1024) /* UBR Work Queue */ #define F_UBR_WQ_START_1M (160*1024) /* UBR Work Queue */ #define F_EVC_START (24*1024) /* Extended VC table start */ #define F_EVC_START_128K (24*1024) /* Extended VC table start */ #define F_EVC_START_512K (96*1024) /* Extended VC table start */ #define F_EVC_START_1M (192*1024) /* Extended VC table start */ /* * R-FRED control memory layout. * Numbers are offset from the start of this memory */ #define R_DESC_START 0 /* Descriptor table start */ #define R_LFQ_START ( 8*1024) /* Large buffer free queue start*/ #define R_SFQ_START ( 9*1024) /* Small buffer free queue start*/ #define R_PCQ_START (10*1024) /* Packet complete queue start */ #define R_EXCP_START (11*1024) /* Exception queue start */ #define R_REASSM_START (16*1024) /* Reassembly table start */ #define R_VC_START (32*1024) /* VC table start */ #define R_LFQ_START_128K ( 8*1024) /* Large buffer free queue start*/ #define R_PCQ_START_128K (10*1024) /* Packet complete queue start */ #define R_EXCP_START_128K (11*1024) /* Exception queue start */ #define R_REASSM_START_128K (16*1024) /* Reassembly table start */ #define R_VC_START_128K (24*1024) /* VC table start */ #define R_LFQ_START_512K (32*1024) /* Large buffer free queue start*/ #define R_PCQ_START_512K (40*1024) /* Packet complete queue start */ #define R_EXCP_START_512K (44*1024) /* Exception queue start */ #define R_REASSM_START_512K (64*1024) /* Reassembly table start */ #define R_VC_START_512K (96*1024) /* VC table start */ #define R_LFQ_START_1M (64*1024) /* Large buffer free queue start*/ #define R_PCQ_START_1M (80*1024) /* Packet complete queue start */ #define R_EXCP_START_1M (88*1024) /* Exception queue start */ #define R_REASSM_START_1M (128*1024) /* Reassembly table start */ #define R_VC_START_1M (192*1024) /* VC table start */ /* Atlantic only */ #define R_ABR_VC_START (32*1024) /* ABR VC table start */ #define R_ABR_VC_START_128K (32*1024) /* ABR VC table start */ #define R_ABR_VC_START_512K (128*1024) /* ABR VC table start */ #define R_ABR_VC_START_1M (256*1024) /* ABR VC table start */ /* * F-FRED sizes */ #define F_NUM_VC 1024 /* Size of Tx VC table */ #define F_NUM_VC_128K 1024 /* Size of Tx VC table */ #define F_NUM_VC_512K 4096 /* Size of Tx VC table */ #define F_NUM_VC_1M 8192 /* Size of Tx VC table */ /* Atlantic only */ #define F_UBR_TBL 2048 /* Size of UBR table */ #define F_UBR_TBL_128K 2048 /* Size of UBR table */ #define F_UBR_TBL_512K 8192 /* Size of UBR table */ #define F_UBR_TBL_1M 16384 /* Size of UBR table */ #define F_UBR_WQ 2048 /* Size of UBR wait queue */ #define F_UBR_WQ_128K 2048 /* Size of UBR wait queue */ #define F_UBR_WQ_512K 8192 /* Size of UBR wait queue */ #define F_UBR_WQ_1M 16384 /* Size of UBR wait queue */ #define F_ABR_TBL 1024 /* Size of ABR table */ #define F_ABR_TBL_128K 1024 /* Size of ABR table */ #define F_ABR_TBL_512K 4096 /* Size of ABR table */ #define F_ABR_TBL_1M 8192 /* Size of ABR table */ #define F_ABR_WQ 1024 /* Size of ABR wait queue */ #define F_ABR_WQ_128K 1024 /* Size of ABR wait queue */ #define F_ABR_WQ_512K 4096 /* Size of ABR wait queue */ #define F_ABR_WQ_1M 8192 /* Size of ABR wait queue */ /* * R-FRED sizes * * NOTE: Reassembly table size must be a multiple of 512 bytes for * the timeout stuff to work properly. */ #define R_NUM_VC 1024 /* Size of Rx VC table */ #define R_NUM_VC_128K 1024 /* Size of Rx VC table */ #define R_NUM_VC_512K 4096 /* Size of Rx VC table */ #define R_NUM_VC_1M 8192 /* Size of Rx VC table */ #define R_REASSM_SIZE R_NUM_VC /* Entries in reassembly table */ #define R_REASSM_SIZE_128K 1024 /* Entries in reassembly table */ #define R_REASSM_SIZE_512K 4096 /* Entries in reassembly table */ #define R_REASSM_SIZE_1M 8192 /* Entries in reassembly table */ #define NUM_RX_EXCP 32 /* Size of exception queue */ #define R_VC_MASK 0x07ff /* VC mask */ /* * MISC drfines */ #define LOCAL_VCI 8 /* For local driver requests */ #endif _IA_CONF_H