/* ia_flip.h */ /* Copyright (c) 2000 James M. Westall, Dept of Computer Science, * Clemson University, Clemson SC 29634 USA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * To obtain a copy of the GNU General Public License write to the * Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * This software is derived from software developed by the Interphase * corporation and released by them in September 2000. The software * released by Interphase carried the following copyright notice: * * * Copyright (C) 1993 * Interphase Corporation, Dallas, TX 75234 * All Rights Reserved * * This code contains confidential information and trade secrets of * Interphase Corporation which shall not be reproduced or transferred * to other programs or disclosed to others or used for manufacturing * or any other purpose without prior written permission of Interphase * Corporation. Use of copyright notice is precautionary and does not * imply publication or intent thereof. */ /* * $Id: ia_flip.h,v 1.3 1998/09/24 15:40:23 pwang Exp $ * * flipper.h : flipper control register definitions * * This header file defines 3 areas... * 1. Internal "Run Time" Register Set * 2. Configuration Register Set * 3. DMA Descriptor (DLE) is defined * * Reference : Flipper Functional Specification */ #include "ia_types.h" #ifndef FLIPPER_H #define FLIPPER_H #define TRANSMIT_DIR 0x00 /* data moves sys to board */ #define RECEIVE_DIR 0x01 /* data moves board to sys */ #define FLIPPER_CELL_SIZE 56 /* 48 bytes + 4 address + 4 count */ /* * Device offsets */ /* Pre-Atlantic */ #define FFRED_OFFSET 0x00000 /* FFRED registers */ #define RFRED_OFFSET 0x01000 /* RFRED registers */ #define FECR_OFFSET 0x02000 /* Front end control register */ #define SUNI_OFFSET 0x02800 /* SUNI registers */ #define FLIP_OFFSET 0x03000 /* Flipper Internal registers */ #define CONFIG_OFFSET 0x04000 /* Configuration registers */ #define TX_TC_OFFSET 0x05000 /* Tx transaction counter */ #define RX_TC_OFFSET 0x05004 /* Rx transaction counter */ #define FFRED_MEM_OFFSET 0x10000 /* FFRED control RAM */ #define RFRED_MEM_OFFSET 0x20000 /* RFRED control RAM */ /* Atlantic */ #define FFREDN_OFFSET 0x02000 /* FFRED registers */ #define RFREDN_OFFSET 0x03000 /* RFRED registers */ #define SUNIN_OFFSET 0x04000 /* SUNI registers */ #define TXN_TC_OFFSET 0x04800 /* Tx transaction counter */ #define RXN_TC_OFFSET 0x04a00 /* Rx transaction counter */ #define TX_LIST_PTR 0x04c00 /* Tx list pointer */ #define RX_LIST_PTR 0x04e00 /* Rx list pointer */ #define FLIPN_OFFSET 0x01000 /* Flipper Internal registers */ #define CONFIGN_OFFSET 0x00000 /* Configuration registers */ #define FFREDN_MEM_OFFSET 0x10000 /* FFRED control RAM */ #define RFREDN_MEM_OFFSET 0x20000 /* RFRED control RAM */ #define FFREDN_MEM_OFFSET_128K 0x10000 /* FFRED control RAM */ #define RFREDN_MEM_OFFSET_128K 0x20000 /* RFRED control RAM */ #define FFREDN_MEM_OFFSET_512K 0x40000 /* FFRED control RAM */ #define RFREDN_MEM_OFFSET_512K 0x80000 /* RFRED control RAM */ #define FFREDN_MEM_OFFSET_1M 0x80000 /* FFRED control RAM */ #define RFREDN_MEM_OFFSET_1M 0x100000 /* RFRED control RAM */ /* * internal registers */ typedef struct _fl_internal { uint_t fl_ctrl; /* general purpose flipper control */ uint_t fl_status; /* interrupt status */ uint_t fl_mac1; /* lower 32 bits of mac */ uint_t fl_mac2; /* ID etc & upper 16 bits of mac */ uint_t fl_ext_reset; uint_t fl_int_reset; uint_t fl_fpcnt; uint_t fl_pci_page; /* used for 64 bit addressing */ uint_t fl_transmit_list; /* Pre-Atlantic only */ uint_t fl_receive_list; /* Pre-Atlantic only */ uint_t fl_eeprom_access; uint_t fl_queue_size; uint_t fl_mark_state; /* * the cell_read_ptr, write_ptr, cells_avail, last_addr registers * assume bits 1:0 are 0 */ uint_t fl_cell_read_ptr; uint_t fl_cell_write_ptr; uint_t fl_cells_avail; uint_t fl_last_addr; } fl_internal_t; #define FL_INTERNAL fl_internal_t #define ia_flip_t fl_internal_t /* * Control Register Bits */ /* access masks */ #define FL_CTRL_RESET 0x80000000 #define FL_CTRL_LED 0x40000000 #define FL_CTRL_ERRMASK 0x00400000 #define FL_CTRL_MARKMASK 0x00200000 #define FL_CTRL_DLETMASK 0x00100000 #define FL_CTRL_DLERMASK 0x00080000 #define FL_CTRL_FEMASK 0x00040000 #define FL_CTRL_FFREDMASK 0x00020000 #define FL_CTRL_RFREDMASK 0x00010000 #define FL_CTRL_FSPREEMPT 0x00002000 #define FL_CTRL_INTERMIX 0x00001000 #define FL_CTRL_DUALAD 0x00000800 #define FL_CTRL_USEFPCNT 0x00000400 /* Pre-Atlantic only */ #define FL_CTRL_TEST 0x00000200 #define FL_CTRL_B48 0x00000100 #define FL_CTRL_B08 0x00000080 #define FL_CTRL_B16 0x00000040 #define FL_CTRL_B32 0x00000020 #define FL_CTRL_B64 0x00000010 /* Atlantic only */ #define FL_CTRL_B128_N 0x00000200 #define FL_CTRL_B64_N 0x00000100 #define FL_CTRL_B48_N 0x00000080 #define FL_CTRL_B32_N 0x00000040 #define FL_CTRL_B16_N 0x00000020 #define FL_CTRL_B08_N 0x00000010 /* Common */ #define FL_CTRL_PRIORITY_MSK 0x0000000C #define FL_CTRL_CELLMODE 0x00000002 #define FL_CTRL_MEMLINE 0x00000001 /* * Status Register Bits * These are interupt status indicators. */ #define FL_STAT_ERRINT 0x00000040 #define FL_STAT_MARKINT 0x00000020 #define FL_STAT_DLETINT 0x00000010 #define FL_STAT_DLERINT 0x00000008 #define FL_STAT_FEINT 0x00000004 #define FL_STAT_FFREDINT 0x00000002 #define FL_STAT_RFREDINT 0x00000001 #define FL_STAT_RESERVED 0xFFFFFF80 /* * MAC 2 Register */ #define FL_MAC2_REV 0xF0000000 #define FL_MAC2_ID 0x0FF00000 #define FL_MAC2_MANUF 0x000F0000 #define FL_MAC2_MAC_MSK 0x0000FFFF /* use with fl_mac1 */ /* * Flipper FPCNT */ #define FL_FPCNT 0x0000FF00 #define FL_FTHRESH 0x000000FF /* * Flipper Transmit List Address Register */ #define FL_TLA_LAB_MSK 0xFFFFF000 #define FL_TLA_LAP_MSK 0x00000FF0 /* * Flipper Receive List Address Register */ #define FL_RLA_LAB_MSK 0xFFFFF000 #define FL_RLA_LAP_MSK 0x00000FF0 /* * Flipper EEPROM Access Register */ #define FL_EEPROM_DI 0x00000008 /* data in */ #define FL_EEPROM_DO 0x00000004 /* data out */ #define FL_EEPROM_CS 0x00000002 /* chip select */ #define FL_EEPROM_CLK 0x00000001 /* clock */ /* * Flipper Queue Size Register */ #define FL_QSIZE_MSK 0x00FFFFFC /* * Flipper Mark State */ #define FL_MSTATE_MSK 0x00000001 /* * Flipper Transaction Counter Masks */ #define FL_TXACTCNT_MSK 0x000000FF #define FL_RXACTCNT_MSK 0x000000FF /*----------------------------------------------------------------------------*/ /* * Configuration Registers * * This structure is defined in the PCI Local Bus Spec. 2.0 * * individual register definitions follow... * */ typedef struct _fl_config { uint_t fl_cfg_id; uint_t fl_cfg_cmd_status; uint_t fl_cfg_class_rev; uint_t fl_cfg_latency; uint_t fl_cfg_memory_address; uint_t fl_cfg_fill0[7]; uint_t fl_cfg_rombase; uint_t fl_cfg_fill1[2]; uint_t fl_cfg_interrupt; }fl_config_t; #define FL_CONFIG fl_config_t /* * individual words/bytes spelled out */ typedef struct _fl_config_2 { ushort_t fl_vend_id; /* 0x00 */ ushort_t fl_dev_id; ushort_t fl_cmd; /* 0x04 */ ushort_t fl_status; uchar_t fl_revid; /* 0x08 */ uchar_t fl_class0; uchar_t fl_class1; uchar_t fl_class2; uchar_t pci_cache_line; /* PCI Cache Line Size Register */ uchar_t pci_lat_tmr; /* PCI Latency Timer Register */ uchar_t pci_header; /* PCI Header Type Register */ uchar_t rsvd_1; uint_t fl_cfg_baseaddr0; /* 0x10 */ uint_t fl_cfg_baseaddr1; uint_t fl_cfg_baseaddr2; uint_t fl_cfg_baseaddr3; uint_t fl_cfg_baseaddr4; uint_t fl_cfg_baseaddr5; uint_t fl_rsrvd0; uint_t fl_rsrvd1; uint_t fl_cfg_rombase; uint_t fl_rsrvd2; uint_t fl_rsrvd3; uchar_t fl_intline; uchar_t fl_intpin; uchar_t fl_mingnt; uchar_t fl_maxlat; }fl_config_2_t; #define FL_CONFIG_2 fl_config_2_t /* * Immediate offsets to Configuration Space * Configuration ID Register */ #define VENDID_OFFSET 0x0000 /* bytes 0,1 */ #define DEVID_OFFSET 0x0002 /* bytes 2,3 */ #define CMD_OFFSET 0x0004 #define STATUS_OFFSET 0x0006 #define CLASS_REV_OFFSET 0x0008 #define INTR_OFFSET 0x003C #define MEMADDR_OFFSET 0x0010 #define ROMADDR_OFFSET 0x0032 #define PCI_CONFIG_DEVID 0x0001 /* Interphase Product ID */ #define PCI_CONFIG_DEVID_N 0x0008 /* Interphase Product ID */ #define PCI_CONFIG_VENDID 0x107E /* assigned by PCI SIG */ #define PCI_BASE_CLASS 0x02 /* For network adapter */ #define PCI_SUB_CLASS 0x03 /* For ATM adapter */ #define PCI_CLASS_MASK 0xffff0000 /* Mask for class */ #define PCI_CLASS 0x02030000 /* Value for class in word */ #define PCI_IRQ_MASK 0x000000ff /* Value for IRQ in word */ /* * new hardware configuration bit definition */ #define HW_CONF_OFFSET 0x002A #define HW_CONF_OFFSET_ATLANTIC 0x0032 #define MAC1_HI_OFFSET 0x0024 #define MAC1_LO_OFFSET 0x0026 #define MAC2_OFFSET 0x002A #define MAC_DEFAULT1_OFFSET 0x002C #define MAC_DEFAULT2_OFFSET 0x002E #define MAC_DEFAULT3_OFFSET 0x0030 #define MEM_SIZE_MASK 0x000F /* mask of 4 bits defining memory size*/ #define MEM_SIZE_128K 0x0000 /* board has 128k buffer */ #define MEM_SIZE_512K 0x0001 /* board has 512K of buffer */ #define MEM_SIZE_1M 0x0002 /* board has 1M of buffer */ /* 0x3 to 0xF are reserved for future */ #define FE_MASK 0x00F0 /* mask of 4 bits defining FE type */ #define FE_MULTI_MODE 0x0000 /* 155 MBit multimode fiber */ #define FE_SINGLE_MODE 0x0010 /* 155 MBit single mode laser */ #define FE_UTP_OPTION 0x0020 /* 155 MBit UTP front end */ #define FE_25MBIT_PHY 0x0040 /* 25 MBit front end */ #define FE_DS3_PHY 0x0080 /* DS3 */ #define FE_E3_PHY 0x0090 /* E3 */ /*----------------------------------------------------------------------------*/ /* * EEPROM Definition * This is the eeprom that loads the flipper with its initial registers * settings after a reset. * * 93C46 : Atmel * part length : 16 bits * 64 : 1024 bits */ typedef struct _fl_eeprom { ushort_t fl_ee_devid; /* 170 */ ushort_t fl_ee_vendid; ushort_t fl_ee_status; ushort_t fl_ee_cmd; ushort_t fl_ee_class; ushort_t fl_ee_progif; ushort_t fl_ee_header_type; ushort_t fl_ee_latency; ushort_t fl_ee_membase_hi; ushort_t fl_ee_membase_lo; ushort_t fl_ee_rombase_hi; ushort_t fl_ee_rombase_lo; ushort_t fl_ee_interrupt_hi; ushort_t fl_ee_interrupt_lo; ushort_t fl_ee_mac1_hi; ushort_t fl_ee_mac1_lo; ushort_t fl_ee_id; ushort_t fl_ee_mac2; /* 187 */ ushort_t fl_ee_unused[46]; }fl_eeprom_t; #define FL_EEPROM fl_eeprom_t /* * ATLANTIC VERSION */ typedef struct _fl_eeprom_atlantic { ushort_t fl_ee_devid; /* 170 */ ushort_t fl_ee_vendid; ushort_t fl_ee_status; ushort_t fl_ee_cmd; ushort_t fl_ee_class; ushort_t fl_ee_progif; ushort_t fl_ee_header_type; ushort_t fl_ee_latency; ushort_t fl_ee_membase_hi; ushort_t fl_ee_membase_lo; ushort_t fl_ee_notused0; ushort_t fl_ee_notused1; ushort_t fl_ee_rombase_hi; ushort_t fl_ee_rombase_lo; ushort_t fl_ee_interrupt_hi; ushort_t fl_ee_interrupt_lo; ushort_t fl_ee_ctrlramsize_hi; ushort_t fl_ee_ctrlramsize_lo; ushort_t fl_ee_mac1_hi; ushort_t fl_ee_mac1_lo; ushort_t fl_ee_id; ushort_t fl_ee_mac2; /* beginning of factory program only region */ ushort_t fl_ee_mac_default1; ushort_t fl_ee_mac_default2; ushort_t fl_ee_mac_default3; ushort_t fl_ee_mac_hw1; /* Hardware Configuration Word 1 */ ushort_t fl_ee_mac_hw2; ushort_t fl_ee_progammed; /* end of factory program only region */ ushort_t fl_ee_os_id; ushort_t fl_ee_os_specific[15]; /* 4 less for atlantic */ ushort_t fl_ee_customer[20]; /* Interphase will not use */ }fl_eeprom_atlantic_t; #define FL_EEPROM_ATLANTIC fl_eeprom_atlantic_t /* * Configuration Command Status Register Bits */ #define CFG_CS_PERR 0x80000000 #define CFG_CS_SERR 0x40000000 #define CFG_CS_RMABORT 0x20000000 #define CFG_CS_RTABORT 0x10000000 #define CFG_CS_STABORT 0x08000000 #define CFG_CS_DEVSEL0 0x04000000 #define CFG_CS_DEVSEL1 0x02000000 #define CFG_CS_DATAPERR 0x01000000 #define CFG_CS_FBBCAP 0x00800000 #define CFG_CS_RESERVED 0x007FFC00 #define CFG_CS_FBBEN 0x00000200 #define CFG_CS_SERREN 0x00000100 #define CFG_CS_ADSTEP 0x00000080 #define CFG_CS_PEREN 0x00000040 #define CFG_CS_VGASNP 0x00000020 #define CFG_CS_MWIEN 0x00000010 #define CFG_CS_SCYEN 0x00000008 #define CFG_CS_BMEN 0x00000004 #define CFG_CS_MEMEN 0x00000002 #define CFG_CS_IOEN 0x00000001 /* * Configuration Class Revision Register Bits */ /* access masks */ #define CFG_CR_BCLASS_MSK 0xFF000000 #define CFG_CR_SCLASS_MSK 0x00FF0000 #define CFG_CR_PROGIF_MSK 0x0000FF00 #define CFG_CR_REV_MSK 0x000000FF /* * Configuration Latency-Type-Cache Register */ /* access masks */ #define CFG_CLTC_HEADER_MSK 0x00FF0000 #define CFG_CLTC_LATENCY_MSK 0x0000FF00 #define CFG_CLTC_CACHSZ_MSK 0x00000070 #define CFG_CLTC_CACHSZ_RSVD 0xFF00008F /* * Configuration Memory Base Address Register */ /* access masks */ #define CFG_MB_BASERW 0xFFFC0000 #define CFG_MB_BASERO 0x0003FFF0 #define CFG_MB_PREFETCH 0x00000008 #define CFG_MB_TYPE 0x00000006 #define CFG_MB_MEMSP 0x00000001 /* * Configuration Expansion Rom Base Address Register */ /* access masks */ #define CFG_EB_BASERW 0xFFFC0000 #define CFG_EB_BASERO 0x0003F800 #define CFG_EB_RESERVED 0x000007FE #define CFG_EB_DECODEN 0x00000001 /* * Configuration Interrupt Register */ /* access masks */ #define CFG_IR_RESERVED 0xFFFF0000 #define CFG_IR_INTLIN 0x0000FF00 #define CFG_IR_INTPIN 0x000000FF /*----------------------------------------------------------------------------*/ /* * DMA List Entry Description */ typedef struct _dle { uint_t dle_sys_addr; uint_t dle_local_addr; uint_t dle_count; ushort_t dle_prq_wr_ptr; ushort_t dle_mode; }dle_t; #define DLE dle_t #define NUM_DLES 256 /* this is how many DLE's the flipper MUST */ /* have in system memory */ /* * dle_mode bit DEFINES */ #define DLE_INT_ENABLE 0x0002 /* 1 = generate interrupt after dma done */ #define DLE_PRQWD 0x0001 /* packet rdy queue write disable, 1 = NO strobe to FFRED Packet Ready Queue 0 = strobe */ #define SIZE_DLE_SPACE (NUM_DLES * sizeof(DLE)) #endif /* _FLIPPER_H */