/* ia_suni.h */ /* Copyright (c) 2000 James M. Westall, Dept of Computer Science, * Clemson University, Clemson SC 29634 USA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * To obtain a copy of the GNU General Public License write to the * Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * This software is derived from software developed by the Interphase * corporation and released by them in September 2000. The software * released by Interphase carried the following copyright notice: * * Copyright (C) 1993 * Interphase Corporation, Dallas, TX 75234 * All Rights Reserved * * This code contains confidential information and trade secrets of * Interphase Corporation which shall not be reproduced or transferred * to other programs or disclosed to others or used for manufacturing * or any other purpose without prior written permission of Interphase * Corporation. Use of copyright notice is precautionary and does not * imply publication or intent thereof. */ /*H * FILE: ia_suni.h * * DESCRIPTION: * This file contains the header information for the PM5345 SUNI. * * FUNCTIONS: * EXPORTED: * * STATIC: * * GLOBAL DATA: * */ #ifndef _IA_SUNI_H #define _IA_SUNI_H typedef struct { uint_t suni_master_reset; /* SUNI Master Reset and Identity */ uint_t suni_master_config; /* SUNI Master Configuration */ uint_t suni_master_intr_stat; /* SUNI Master Interrupt Status */ uint_t suni_reserved1; /* Reserved */ uint_t suni_master_clk_monitor;/* SUNI Master Clock Monitor */ uint_t suni_master_control; /* SUNI Master Clock Monitor */ uint_t suni_reserved2[10]; /* Reserved */ uint_t suni_rsop_control; /* RSOP Control/Interrupt Enable */ uint_t suni_rsop_status; /* RSOP Status/Interrupt States */ uint_t suni_rsop_section_bip8l;/* RSOP Section BIP-8 LSB */ uint_t suni_rsop_section_bip8m;/* RSOP Section BIP-8 MSB */ uint_t suni_tsop_control; /* TSOP Control */ uint_t suni_tsop_diag; /* TSOP Disgnostics */ uint_t suni_tsop_reserved[2]; /* TSOP Reserved */ uint_t suni_rlop_cs; /* RLOP Control/Status */ uint_t suni_rlop_intr; /* RLOP Interrupt Enable/Status */ uint_t suni_rlop_line_bip24l; /* RLOP Line BIP-24 LSB */ uint_t suni_rlop_line_bip24; /* RLOP Line BIP-24 */ uint_t suni_rlop_line_bip24m; /* RLOP Line BIP-24 MSB */ uint_t suni_rlop_line_febel; /* RLOP Line FEBE LSB */ uint_t suni_rlop_line_febe; /* RLOP Line FEBE */ uint_t suni_rlop_line_febem; /* RLOP Line FEBE MSB */ uint_t suni_tlop_control; /* TLOP Control */ uint_t suni_tlop_disg; /* TLOP Disgnostics */ uint_t suni_tlop_reserved[14]; /* TLOP Reserved */ uint_t suni_rpop_cs; /* RPOP Status/Control */ uint_t suni_rpop_intr; /* RPOP Interrupt/Status */ uint_t suni_rpop_reserved; /* RPOP Reserved */ uint_t suni_rpop_intr_ena; /* RPOP Interrupt Enable */ uint_t suni_rpop_reserved1[3]; /* RPOP Reserved */ uint_t suni_rpop_path_sig; /* RPOP Path Signal Label */ uint_t suni_rpop_bip8l; /* RPOP Path BIP-8 LSB */ uint_t suni_rpop_bip8m; /* RPOP Path BIP-8 MSB */ uint_t suni_rpop_febel; /* RPOP Path FEBE LSB */ uint_t suni_rpop_febem; /* RPOP Path FEBE MSB */ uint_t suni_rpop_reserved2[4]; /* RPOP Reserved */ uint_t suni_tpop_cntrl_daig; /* TPOP Control/Disgnostics */ uint_t suni_tpop_pointer_ctrl; /* TPOP Pointer Control */ uint_t suni_tpop_sourcer_ctrl; /* TPOP Source Control */ uint_t suni_tpop_reserved1[2]; /* TPOP Reserved */ uint_t suni_tpop_arb_prtl; /* TPOP Arbitrary Pointer LSB */ uint_t suni_tpop_arb_prtm; /* TPOP Arbitrary Pointer MSB */ uint_t suni_tpop_reserved2; /* TPOP Reserved */ uint_t suni_tpop_path_sig; /* TPOP Path Signal Lable */ uint_t suni_tpop_path_status; /* TPOP Path Status */ uint_t suni_tpop_reserved3[6]; /* TPOP Reserved */ uint_t suni_racp_cs; /* RACP Control/Status */ uint_t suni_racp_intr; /* RACP Interrupt Enable/Status */ uint_t suni_racp_hdr_pattern; /* RACP Match Header Pattern */ uint_t suni_racp_hdr_mask; /* RACP Match Header Mask */ uint_t suni_racp_corr_hcs; /* RACP Correctable HCS Error Count */ uint_t suni_racp_uncorr_hcs; /* RACP Uncorrectable HCS Error Count */ uint_t suni_racp_reserved[10]; /* RACP Reserved */ uint_t suni_tacp_control; /* TACP Control */ uint_t suni_tacp_idle_hdr_pat; /* TACP Idle Cell Header Pattern */ uint_t suni_tacp_idle_pay_pay; /* TACP Idle Cell Payld Octet Pattern */ uint_t suni_tacp_reserved[5]; /* TACP Reserved */ uint_t suni_reserved3[24]; /* Reserved */ uint_t suni_master_test; /* SUNI Master Test */ uint_t suni_reserved_test; /* SUNI Reserved for Test */ } ia_suni_t; typedef struct _suni_pm7345_t { uint_t suni_config; /* SUNI Configuration */ uint_t suni_intr_enbl; /* SUNI Interrupt Enable */ uint_t suni_intr_stat; /* SUNI Interrupt Status */ uint_t suni_control; /* SUNI Control */ uint_t suni_id_reset; /* SUNI Reset and Identity */ uint_t suni_data_link_ctrl; uint_t suni_rboc_conf_intr_enbl; uint_t suni_rboc_stat; uint_t suni_ds3_frm_cfg; uint_t suni_ds3_frm_intr_enbl; uint_t suni_ds3_frm_intr_stat; uint_t suni_ds3_frm_stat; uint_t suni_rfdl_cfg; uint_t suni_rfdl_enbl_stat; uint_t suni_rfdl_stat; uint_t suni_rfdl_data; uint_t suni_pmon_chng; uint_t suni_pmon_intr_enbl_stat; uint_t suni_reserved1[0x13-0x11]; uint_t suni_pmon_lcv_evt_cnt_lsb; uint_t suni_pmon_lcv_evt_cnt_msb; uint_t suni_pmon_fbe_evt_cnt_lsb; uint_t suni_pmon_fbe_evt_cnt_msb; uint_t suni_pmon_sez_det_cnt_lsb; uint_t suni_pmon_sez_det_cnt_msb; uint_t suni_pmon_pe_evt_cnt_lsb; uint_t suni_pmon_pe_evt_cnt_msb; uint_t suni_pmon_ppe_evt_cnt_lsb; uint_t suni_pmon_ppe_evt_cnt_msb; uint_t suni_pmon_febe_evt_cnt_lsb; uint_t suni_pmon_febe_evt_cnt_msb; uint_t suni_ds3_tran_cfg; uint_t suni_ds3_tran_diag; uint_t suni_reserved2[0x23-0x21]; uint_t suni_xfdl_cfg; uint_t suni_xfdl_intr_st; uint_t suni_xfdl_xmit_data; uint_t suni_xboc_code; uint_t suni_splr_cfg; uint_t suni_splr_intr_en; uint_t suni_splr_intr_st; uint_t suni_splr_status; uint_t suni_splt_cfg; uint_t suni_splt_cntl; uint_t suni_splt_diag_g1; uint_t suni_splt_f1; uint_t suni_cppm_loc_meters; uint_t suni_cppm_chng_of_cppm_perf_meter; uint_t suni_cppm_b1_err_cnt_lsb; uint_t suni_cppm_b1_err_cnt_msb; uint_t suni_cppm_framing_err_cnt_lsb; uint_t suni_cppm_framing_err_cnt_msb; uint_t suni_cppm_febe_cnt_lsb; uint_t suni_cppm_febe_cnt_msb; uint_t suni_cppm_hcs_err_cnt_lsb; uint_t suni_cppm_hcs_err_cnt_msb; uint_t suni_cppm_idle_un_cell_cnt_lsb; uint_t suni_cppm_idle_un_cell_cnt_msb; uint_t suni_cppm_rcv_cell_cnt_lsb; uint_t suni_cppm_rcv_cell_cnt_msb; uint_t suni_cppm_xmit_cell_cnt_lsb; uint_t suni_cppm_xmit_cell_cnt_msb; uint_t suni_rxcp_ctrl; uint_t suni_rxcp_fctrl; uint_t suni_rxcp_intr_en_sts; uint_t suni_rxcp_idle_pat_h1; uint_t suni_rxcp_idle_pat_h2; uint_t suni_rxcp_idle_pat_h3; uint_t suni_rxcp_idle_pat_h4; uint_t suni_rxcp_idle_mask_h1; uint_t suni_rxcp_idle_mask_h2; uint_t suni_rxcp_idle_mask_h3; uint_t suni_rxcp_idle_mask_h4; uint_t suni_rxcp_cell_pat_h1; uint_t suni_rxcp_cell_pat_h2; uint_t suni_rxcp_cell_pat_h3; uint_t suni_rxcp_cell_pat_h4; uint_t suni_rxcp_cell_mask_h1; uint_t suni_rxcp_cell_mask_h2; uint_t suni_rxcp_cell_mask_h3; uint_t suni_rxcp_cell_mask_h4; uint_t suni_rxcp_hcs_cs; uint_t suni_rxcp_lcd_cnt_threshold; uint_t suni_reserved3[0x57-0x54]; uint_t suni_txcp_ctrl; uint_t suni_txcp_intr_en_sts; uint_t suni_txcp_idle_pat_h1; uint_t suni_txcp_idle_pat_h2; uint_t suni_txcp_idle_pat_h3; uint_t suni_txcp_idle_pat_h4; uint_t suni_txcp_idle_pat_h5; uint_t suni_txcp_idle_payload; uint_t suni_e3_frm_fram_options; uint_t suni_e3_frm_maint_options; uint_t suni_e3_frm_fram_intr_enbl; uint_t suni_e3_frm_fram_intr_ind_stat; uint_t suni_e3_frm_maint_intr_enbl; uint_t suni_e3_frm_maint_intr_ind; uint_t suni_e3_frm_maint_stat; uint_t suni_reserved4; uint_t suni_e3_tran_fram_options; uint_t suni_e3_tran_stat_diag_options; uint_t suni_e3_tran_bip_8_err_mask; uint_t suni_e3_tran_maint_adapt_options; uint_t suni_ttb_ctrl; uint_t suni_ttb_trail_trace_id_stat; uint_t suni_ttb_ind_addr; uint_t suni_ttb_ind_data; uint_t suni_ttb_exp_payload_type; uint_t suni_ttb_payload_type_ctrl_stat; uint_t suni_pad5[0x7f-0x71]; uint_t suni_master_test; uint_t suni_pad6[0xff-0x80]; }suni_pm7345_t; #define SUNI_PM7345_T suni_pm7345_t /* * SUNI Master Reset and Identity */ #define SUNI_RESET 0x80 /* Suni reset */ #define SUNI_PM7345 0x20 /* Suni chip type */ #define SUNI_PM5346 0x30 /* Suni chip type */ /* * SUNI_PM7345 Configuration */ #define SUNI_PM7345_CLB 0x01 /* Cell loopback */ #define SUNI_PM7345_PLB 0x02 /* Payload loopback */ #define SUNI_PM7345_DLB 0x04 /* Diagnostic loopback */ #define SUNI_PM7345_LLB 0x80 /* Line loopback */ #define SUNI_PM7345_E3ENBL 0x40 /* E3 enable bit */ #define SUNI_PM7345_LOOPT 0x10 /* LOOPT enable bit */ #define SUNI_PM7345_FIFOBP 0x20 /* FIFO bypass */ #define SUNI_PM7345_FRMRBP 0x08 /* Framer bypass */ /* * SUNI Master Configuration */ /* SUNI only */ #define SUNI_GPINE 0x80 /* GPINE interrupt enable */ /* Common */ #define SUNI_AUTOFEBE 0x40 /* Send FEBE errors */ #define SUNI_AUTOFERF 0x20 /* Send FERF errors */ #define SUNI_AUTOYEL 0x10 /* Send STS path yellow alarm */ #define SUNI_TCAINV 0x08 /* 1 = TCA active low */ #define SUNI_RCAINV 0x04 /* 1 = RCA active low */ /* SUNI Only */ #define SUNI_MODE_MASK 0x03 /* Select STS-1/STS-3c/STS-12 */ /* SUNI-lite only */ #define SUNI_RXDINV 0x02 /* 1 = RXD+ active low */ /* * SUNI Master Interrupt Status */ /* SUNI Only */ #define SUNI_GPINV 0x80 /* State of GPIN input */ #define SUNI_PFERFI 0x40 /* FERF error */ #define SUNI_GPINI 0x20 /* Transition on GPIN input */ /* SUNI-lite only */ #define SUNI_TROOLI 0x80 /* Tx data out of lock interrupt*/ #define SUNI_LCDI 0x40 /* State change: loss of cell del*/ #define SUNI_RDOOLI 0x20 /* Rx data out of lock interrupt*/ /* Common */ #define SUNI_TACPI 0x10 /* TACP interrupt */ #define SUNI_RACPI 0x08 /* RACP interrupt */ #define SUNI_RPOPI 0x04 /* RPOP interrupt */ #define SUNI_RLOPI 0x02 /* RLOP interrupt */ #define SUNI_RSOPI 0x01 /* RSOP interrupt */ /* * SUNI Master Clock Monitor */ /* SUNI-lite only */ #define SUNI_RRCLKA 0x08 /* Moniter RRCLK+- input */ #define SUNI_TRCLKA 0x04 /* Moniter TRCLK+- input */ /* Common */ #define SUNI_RCLKA 0x02 /* Moniter RCLK output */ #define SUNI_POCLKA 0x01 /* Moniter POCLK input */ /* * SUNI Master Control */ /* SUNI only */ #define SUNI_PFERFE 0x80 /* PFERFE interrupt enable */ #define SUNI_PFERFV 0x40 /* State of FERF in receive stream */ #define SUNI_TPFERF 0x20 /* Transmit PATH FERF */ /* SUNI-lite only */ #define SUNI_LCDE 0x80 /* Enable LCD interrupt */ #define SUNI_LCDV 0x40 /* LCD state */ #define SUNI_FIXPTR 0x20 /* Disable tx payload ptr adjust*/ /* Common */ #define SUNI_LLE 0x04 /* SUNI line loopkack */ #define SUNI_DLE 0x02 /* SUNI disgnostics loopkack */ #define SUNI_LOOPT 0x01 /* Derive Tx clock from RXCI+/RXCI- */ /* * RSOP Control/Interrupt Enable */ #define SUNI_DDS 0x40 /* Disable descrambling */ #define SUNI_FOOF 0x20 /* Force RSOP out of frame */ #define SUNI_BIPEE 0x08 /* Enable BIP-8 error intr */ #define SUNI_LOSE 0x04 /* Enable loss of signal intr */ #define SUNI_LOFE 0x02 /* Enable loss of frame intr */ #define SUNI_OOFE 0x01 /* Enable out of frame intr */ /* * DS3 FRMR Interrupt Enable */ #define SUNI_DS3_COFAE 0x80 /* Enable change of frame align */ #define SUNI_DS3_REDE 0x40 /* Enable DS3 RED state intr */ #define SUNI_DS3_CBITE 0x20 /* Enable Appl ID channel intr */ #define SUNI_DS3_FERFE 0x10 /* Enable Far End Receive Failure intr*/ #define SUNI_DS3_IDLE 0x08 /* Enable Idle signal intr */ #define SUNI_DS3_AISE 0x04 /* Enable Alarm Indication signal intr*/ #define SUNI_DS3_OOFE 0x02 /* Enable Out of frame intr */ #define SUNI_DS3_LOSE 0x01 /* Enable Loss of signal intr */ /* * DS3 FRMR Status */ #define SUNI_DS3_ACE 0x80 /* Additional Configuration Reg */ #define SUNI_DS3_REDV 0x40 /* DS3 RED state */ #define SUNI_DS3_CBITV 0x20 /* Application ID channel state */ #define SUNI_DS3_FERFV 0x10 /* Far End Receive Failure state*/ #define SUNI_DS3_IDLV 0x08 /* Idle signal state */ #define SUNI_DS3_AISV 0x04 /* Alarm Indication signal state*/ #define SUNI_DS3_OOFV 0x02 /* Out of frame state */ #define SUNI_DS3_LOSV 0x01 /* Loss of signal state */ /* * E3 FRMR Interrupt/Status */ #define SUNI_E3_CZDI 0x40 /* Consecutive Zeros indicator */ #define SUNI_E3_LOSI 0x20 /* Loss of signal intr status */ #define SUNI_E3_LCVI 0x10 /* Line code violation intr */ #define SUNI_E3_COFAI 0x08 /* Change of frame align intr */ #define SUNI_E3_OOFI 0x04 /* Out of frame intr status */ #define SUNI_E3_LOS 0x02 /* Loss of signal state */ #define SUNI_E3_OOF 0x01 /* Out of frame state */ /* * E3 FRMR Maintenance Status */ #define SUNI_E3_AISD 0x80 /* Alarm Indication signal state*/ #define SUNI_E3_FERF_RAI 0x40 /* FERF/RAI indicator */ #define SUNI_E3_FEBE 0x20 /* Far End Block Error indicator*/ /* * RSOP Status/Interrupt Status */ #define SUNI_BIPEI 0x40 /* BIP-8 interrupt status */ #define SUNI_LOSI 0x20 /* Loss of signal intr status */ #define SUNI_LOFI 0x10 /* Loss of frame intr status */ #define SUNI_OOFI 0x08 /* Out of frame intr status */ #define SUNI_LOSV 0x04 /* Loss of signal state */ #define SUNI_LOFV 0x02 /* Loss of frame state */ #define SUNI_OOFV 0x01 /* Out of frame state */ /* * RLOP Control */ #define SUNI_LAISV 0x02 /* Line alarm indication signal */ #define SUNI_FERFV 0x01 /* Far end receive failure state*/ /* * RLOP Interrupt Enable/Status */ #define SUNI_FEBEE 0x80 /* Intr enable, line far end block err */ #define SUNI_BIP24EE 0x40 /* Intr enable, line BIP-24 err */ #define SUNI_LAISE 0x20 /* Intr enable, AIS state change */ #define SUNI_FERFE 0x10 /* Inre enable, far end rx fail alarm */ #define SUNI_FEBEI 0x08 /* Status, line far end block err */ #define SUNI_BIP24EI 0x04 /* Status, line BIP-24 err */ #define SUNI_LAISI 0x02 /* Status, AIS state change */ #define SUNI_FERFI 0x01 /* Status, far end rx fail alarm */ /* * RPOP Control/Status */ #define SUNI_LOP 0x20 /* Loss of "Normal pointer value" */ #define SUNI_PAIS 0x08 /* Path AIS */ #define SUNI_PYEL 0x04 /* Path yellow alarm */ /* * RPOP Interrupt/Status */ #define SUNI_PSLI 0x80 /* LOP interrupt */ #define SUNI_LOPI 0x20 /* Path LOP interrupt */ #define SUNI_PAISI 0x08 /* Path AIS interrupt */ #define SUNI_PYELI 0x04 /* Path yellow alarm interrupt */ #define SUNI_PBIPEI 0x02 /* Path BIP-8 error interrupt */ #define SUNI_PFEBEI 0x01 /* Path FEBE interrupt */ /* * RPOP Interrupt Enable */ #define SUNI_PSLE 0x80 /* LOP interrupt enable */ #define SUNI_LOPE 0x20 /* Path LOP interrupt enable */ #define SUNI_PAISE 0x08 /* Path AIS interrupt enable */ #define SUNI_PYELE 0x04 /* Path yellow alarm interrupt enable */ #define SUNI_PBIPEE 0x02 /* Path BIP-8 error interrupt enable */ #define SUNI_PFEBEE 0x01 /* Path FEBE interrupt enable */ /* * RACP Control/Status */ #define SUNI_OOCDV 0x80 /* Cell delineation state */ #define SUNI_PASS 0x20 /* No cell filtering */ #define SUNI_DISCOR 0x10 /* Disable HCS error correction */ #define SUNI_HCSPASS 0x08 /* Pass cell with HEC errors */ #define SUNI_HCSADD 0x04 /* Add coset poly */ #define SUNI_DDSCR 0x02 /* Disable payload descrambling */ #define SUNI_FIFORST 0x01 /* Cell FIFO reset */ /* * RXCP Control/Status */ #define SUNI_DS3_HCSPASS 0x80 /* Pass cell with HEC errors */ #define SUNI_DS3_HCSDQDB 0x40 /* Control octets in HCS calc */ #define SUNI_DS3_HCSADD 0x20 /* Add coset poly */ #define SUNI_DS3_HCK 0x10 /* Control FIFO data path integ chk*/ #define SUNI_DS3_BLOCK 0x08 /* Enable cell filtering */ #define SUNI_DS3_DSCR 0x04 /* Disable payload descrambling */ #define SUNI_DS3_OOCDV 0x02 /* Cell delineation state */ #define SUNI_DS3_FIFORST 0x01 /* Cell FIFO reset */ /* * RACP Interrupt Enable/Status */ #define SUNI_OOCDE 0x80 /* Intr enable, change in CDS */ #define SUNI_HCSE 0x40 /* Intr enable, corr HCS errors */ #define SUNI_FIFOE 0x20 /* Intr enable, unco HCS errors */ #define SUNI_OOCDI 0x10 /* SYNC state */ #define SUNI_CHCSI 0x08 /* Corr. HCS errors detected */ #define SUNI_UHCSI 0x04 /* Uncorr. HCS errors detected */ #define SUNI_FOVRI 0x02 /* FIFO overrun */ #define SUNI_FUDRI 0x01 /* FIFO underrun */ /* * RXCP Interrupt Enable/Status */ #define SUNI_DS3_OOCDE 0x80 /* Intr enable, change in CDS */ #define SUNI_DS3_HCSE 0x40 /* Intr enable, corr HCS errors */ #define SUNI_DS3_FIFOE 0x20 /* Intr enable, unco HCS errors */ #define SUNI_DS3_OOCDI 0x10 /* SYNC state */ #define SUNI_DS3_UHCSI 0x08 /* Uncorr. HCS errors detected */ #define SUNI_DS3_COCAI 0x04 /* Corr. HCS errors detected */ #define SUNI_DS3_FOVRI 0x02 /* FIFO overrun */ #define SUNI_DS3_FUDRI 0x01 /* FIFO underrun */ /* * TSOP Diagnostics used for redundant link. */ #ifdef __RLS__ #define SUNI_DLOS 0x04 /* Force LOS enable */ #define SUNI_DLOS_RELEASE 0x03 /* Force LOS release */ #define IA_SUNI_LOS_TIMER 2500 /* mili sec. (2.5 secs) */ #endif /* __RLS__ */ #ifdef __SNMP__ /* TBD : Set a proper threshold value here. */ #define SYNC_TO_HUNT_THRESHOLD 100 #endif /* __SNMP__ */ #endif /* _IA_SUNI_H */